1/*
2 * Copyright (c) 2020 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f407.dtsi>
8#include <zephyr/dt-bindings/clock/stm32f427_clock.h>
9#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
10
11/ {
12	soc {
13		compatible = "st,stm32f427", "st,stm32f4", "simple-bus";
14
15		pinctrl: pin-controller@40020000 {
16			reg = <0x40020000 0x2C00>;
17
18			gpioj: gpio@40022400 {
19				compatible = "st,stm32-gpio";
20				gpio-controller;
21				#gpio-cells = <2>;
22				reg = <0x40022400 0x400>;
23				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
24			};
25
26			gpiok: gpio@40022800 {
27				compatible = "st,stm32-gpio";
28				gpio-controller;
29				#gpio-cells = <2>;
30				reg = <0x40022800 0x400>;
31				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
32			};
33		};
34
35		uart7: serial@40007800 {
36			compatible = "st,stm32-uart";
37			reg = <0x40007800 0x400>;
38			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
39			resets = <&rctl STM32_RESET(APB1, 30U)>;
40			interrupts = <82 0>;
41			status = "disabled";
42		};
43
44		uart8: serial@40007c00 {
45			compatible = "st,stm32-uart";
46			reg = <0x40007c00 0x400>;
47			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
48			resets = <&rctl STM32_RESET(APB1, 31U)>;
49			interrupts = <83 0>;
50			status = "disabled";
51		};
52
53		spi4: spi@40013400 {
54			compatible = "st,stm32-spi";
55			#address-cells = <1>;
56			#size-cells = <0>;
57			reg = <0x40013400 0x400>;
58			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
59			interrupts = <84 5>;
60			status = "disabled";
61		};
62
63		/* spi5 is present on all STM32F427XX and derivates SoCs except
64		 * some vX variants. Delete node in vX.dtsi.
65		 */
66		 spi5: spi@40015000 {
67			compatible = "st,stm32-spi";
68			#address-cells = <1>;
69			#size-cells = <0>;
70			reg = <0x40015000 0x400>;
71			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
72			interrupts = <85 5>;
73			status = "disabled";
74		};
75
76		/* spi6 is present on all STM32F427XX and derivates SoCs except
77		 * some vX variants. Delete node in vX.dtsi.
78		 */
79		spi6: spi@40015400 {
80			compatible = "st,stm32-spi";
81			#address-cells = <1>;
82			#size-cells = <0>;
83			reg = <0x40015400 0x400>;
84			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
85			interrupts = <86 5>;
86			status = "disabled";
87		};
88
89		fmc: memory-controller@a0000000 {
90			compatible = "st,stm32-fmc";
91			reg = <0xa0000000 0x400>;
92			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
93			status = "disabled";
94
95			sdram: sdram {
96				compatible = "st,stm32-fmc-sdram";
97				#address-cells = <1>;
98				#size-cells = <0>;
99				status = "disabled";
100			};
101		};
102	};
103
104	die_temp: dietemp {
105		io-channels = <&adc1 18>;
106	};
107};
108