1/*
2 * Copyright (c) 2017 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f401.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f411", "st,stm32f4", "simple-bus";
12
13		spi5: spi@40015000 {
14			compatible = "st,stm32-spi";
15			#address-cells = <1>;
16			#size-cells = <0>;
17			reg = <0x40015000 0x400>;
18			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
19			interrupts = <85 5>;
20			status = "disabled";
21		};
22
23		i2s1: i2s@40013000 {
24			compatible = "st,stm32-i2s";
25			#address-cells = <1>;
26			#size-cells = <0>;
27			reg = <0x40013000 0x400>;
28			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
29			interrupts = <35 5>;
30			dmas = <&dma2 3 3 0x400 0x3
31				&dma2 2 3 0x400 0x3>;
32			dma-names = "tx", "rx";
33			status = "disabled";
34		};
35
36		i2s4: i2s@40013400 {
37			compatible = "st,stm32-i2s";
38			#address-cells = <1>;
39			#size-cells = <0>;
40			reg = <0x40013400 0x400>;
41			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
42			interrupts = <84 5>;
43			dmas = <&dma2 1 4 0x400 0x3
44				&dma2 0 4 0x400 0x3>;
45			dma-names = "tx", "rx";
46			status = "disabled";
47		};
48
49		i2s5: i2s@40015000 {
50			compatible = "st,stm32-i2s";
51			#address-cells = <1>;
52			#size-cells = <0>;
53			reg = <0x40015000 0x400>;
54			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
55			interrupts = <85 5>;
56			dmas = <&dma2 6 7 0x400 0x3
57				&dma2 5 7 0x400 0x3>;
58			dma-names = "tx", "rx";
59			status = "disabled";
60		};
61	};
62
63	die_temp: dietemp {
64		io-channels = <&adc1 18>;
65	};
66};
67