1/* 2 * Copyright (c) 2017 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/f3/stm32f3.dtsi> 8#include <zephyr/dt-bindings/adc/stm32f1_adc.h> 9 10/ { 11 soc { 12 compatible = "st,stm32f373", "st,stm32f3", "simple-bus"; 13 14 rcc: rcc@40021000 { 15 /* 16 * Use the STM32F1 compatible that define the same ADC 17 * prescaler in the RCC register 18 */ 19 compatible = "st,stm32f1-rcc"; 20 }; 21 22 pinctrl: pin-controller@48000000 { 23 gpioe: gpio@48001000 { 24 compatible = "st,stm32-gpio"; 25 gpio-controller; 26 #gpio-cells = <2>; 27 reg = <0x48001000 0x400>; 28 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>; 29 }; 30 }; 31 32 i2c2: i2c@40005800 { 33 compatible = "st,stm32-i2c-v2"; 34 clock-frequency = <I2C_BITRATE_STANDARD>; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 reg = <0x40005800 0x400>; 38 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>, 39 /* I2C clock source should always be defined, 40 * even for the default value 41 */ 42 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; 43 interrupts = <33 0>, <34 0>; 44 interrupt-names = "event", "error"; 45 status = "disabled"; 46 }; 47 48 spi2: spi@40003800 { 49 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 reg = <0x40003800 0x400>; 53 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; 54 interrupts = <36 5>; 55 status = "disabled"; 56 }; 57 58 spi3: spi@40003c00 { 59 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 reg = <0x40003c00 0x400>; 63 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; 64 interrupts = <51 5>; 65 status = "disabled"; 66 }; 67 68 timers4: timers@40000800 { 69 compatible = "st,stm32-timers"; 70 reg = <0x40000800 0x400>; 71 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; 72 resets = <&rctl STM32_RESET(APB1, 2U)>; 73 interrupts = <30 0>; 74 interrupt-names = "global"; 75 st,prescaler = <0>; 76 status = "disabled"; 77 78 pwm { 79 compatible = "st,stm32-pwm"; 80 status = "disabled"; 81 #pwm-cells = <3>; 82 }; 83 }; 84 85 timers5: timers@40000c00 { 86 compatible = "st,stm32-timers"; 87 reg = <0x40000c00 0x400>; 88 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; 89 resets = <&rctl STM32_RESET(APB1, 3U)>; 90 interrupts = <50 0>; 91 interrupt-names = "global"; 92 st,prescaler = <0>; 93 status = "disabled"; 94 95 pwm { 96 compatible = "st,stm32-pwm"; 97 status = "disabled"; 98 #pwm-cells = <3>; 99 }; 100 }; 101 102 timers12: timers@40001800 { 103 compatible = "st,stm32-timers"; 104 reg = <0x40001800 0x400>; 105 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>; 106 resets = <&rctl STM32_RESET(APB1, 6U)>; 107 interrupts = <43 0>; 108 interrupt-names = "global"; 109 st,prescaler = <0>; 110 status = "disabled"; 111 112 pwm { 113 compatible = "st,stm32-pwm"; 114 status = "disabled"; 115 #pwm-cells = <3>; 116 }; 117 }; 118 119 timers13: timers@40001c00 { 120 compatible = "st,stm32-timers"; 121 reg = <0x40001c00 0x400>; 122 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>; 123 resets = <&rctl STM32_RESET(APB1, 7U)>; 124 interrupts = <44 0>; 125 interrupt-names = "global"; 126 st,prescaler = <0>; 127 status = "disabled"; 128 129 pwm { 130 compatible = "st,stm32-pwm"; 131 status = "disabled"; 132 #pwm-cells = <3>; 133 }; 134 }; 135 136 timers14: timers@40002000 { 137 compatible = "st,stm32-timers"; 138 reg = <0x40002000 0x400>; 139 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; 140 resets = <&rctl STM32_RESET(APB1, 8U)>; 141 interrupts = <45 0>; 142 interrupt-names = "global"; 143 st,prescaler = <0>; 144 status = "disabled"; 145 146 pwm { 147 compatible = "st,stm32-pwm"; 148 status = "disabled"; 149 #pwm-cells = <3>; 150 }; 151 }; 152 153 timers18: timers@40009c00 { 154 compatible = "st,stm32-timers"; 155 reg = <0x40009c00 0x400>; 156 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>; 157 resets = <&rctl STM32_RESET(APB1, 9U)>; 158 interrupts = <27 0>; 159 interrupt-names = "global"; 160 st,prescaler = <0>; 161 status = "disabled"; 162 163 pwm { 164 compatible = "st,stm32-pwm"; 165 status = "disabled"; 166 #pwm-cells = <3>; 167 }; 168 }; 169 170 timers19: timers@40015c00 { 171 compatible = "st,stm32-timers"; 172 reg = <0x40015c00 0x400>; 173 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>; 174 resets = <&rctl STM32_RESET(APB2, 19U)>; 175 interrupts = <78 0>; 176 interrupt-names = "global"; 177 st,prescaler = <0>; 178 status = "disabled"; 179 180 pwm { 181 compatible = "st,stm32-pwm"; 182 status = "disabled"; 183 #pwm-cells = <3>; 184 }; 185 }; 186 187 adc1: adc@40012400 { 188 compatible = "st,stm32f1-adc", "st,stm32-adc"; 189 reg = <0x40012400 0x400>; 190 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; 191 interrupts = <18 0>; 192 status = "disabled"; 193 #io-channel-cells = <1>; 194 resolutions = <STM32F1_ADC_RES(12)>; 195 sampling-times = <2 8 14 29 42 56 72 240>; 196 st,adc-sequencer = <FULLY_CONFIGURABLE>; 197 }; 198 199 rtc@40002800 { 200 bbram: backup_regs { 201 compatible = "st,stm32-bbram"; 202 st,backup-regs = <32>; 203 status = "disabled"; 204 }; 205 }; 206 }; 207 208 vref: vref { 209 io-channels = <&adc1 17>; 210 }; 211 212 vbat: vbat { 213 io-channels = <&adc1 18>; 214 }; 215}; 216
