1/* 2 * Copyright (c) 2017 I-SENSE group of ICCS 3 * 4 * SoC device tree include for STM32F103xC SoCs 5 * where 'x' is replaced for specific SoCs like {R,V,Z} 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10#include <mem.h> 11#include <st/f1/stm32f103Xb.dtsi> 12 13/ { 14 sram0: memory@20000000 { 15 reg = <0x20000000 DT_SIZE_K(48)>; 16 }; 17 18 soc { 19 flash-controller@40022000 { 20 flash0: flash@8000000 { 21 reg = <0x08000000 DT_SIZE_K(256)>; 22 erase-block-size = <DT_SIZE_K(2)>; 23 }; 24 }; 25 26 uart4: serial@40004c00 { 27 compatible = "st,stm32-uart"; 28 reg = <0x40004c00 0x400>; 29 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; 30 resets = <&rctl STM32_RESET(APB1, 19U)>; 31 interrupts = <52 0>; 32 status = "disabled"; 33 }; 34 35 uart5: serial@40005000 { 36 compatible = "st,stm32-uart"; 37 reg = <0x40005000 0x400>; 38 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; 39 resets = <&rctl STM32_RESET(APB1, 20U)>; 40 interrupts = <53 0>; 41 status = "disabled"; 42 }; 43 44 timers5: timers@40000c00 { 45 compatible = "st,stm32-timers"; 46 reg = <0x40000c00 0x400>; 47 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; 48 resets = <&rctl STM32_RESET(APB1, 3U)>; 49 interrupts = <50 0>; 50 interrupt-names = "global"; 51 st,prescaler = <0>; 52 status = "disabled"; 53 54 pwm { 55 compatible = "st,stm32-pwm"; 56 status = "disabled"; 57 #pwm-cells = <3>; 58 }; 59 }; 60 61 timers6: timers@40001000 { 62 compatible = "st,stm32-timers"; 63 reg = <0x40001000 0x400>; 64 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; 65 resets = <&rctl STM32_RESET(APB1, 4U)>; 66 interrupts = <54 0>; 67 interrupt-names = "global"; 68 st,prescaler = <0>; 69 status = "disabled"; 70 }; 71 72 timers7: timers@40001400 { 73 compatible = "st,stm32-timers"; 74 reg = <0x40001400 0x400>; 75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 76 resets = <&rctl STM32_RESET(APB1, 5U)>; 77 interrupts = <55 0>; 78 interrupt-names = "global"; 79 st,prescaler = <0>; 80 status = "disabled"; 81 }; 82 83 spi3: spi@40003c00 { 84 compatible = "st,stm32-spi"; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 reg = <0X40003c00 0x400>; 88 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; 89 interrupts = <51 5>; 90 status = "disabled"; 91 }; 92 93 dac1: dac@40007400 { 94 compatible = "st,stm32-dac"; 95 reg = <0x40007400 0x400>; 96 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; 97 status = "disabled"; 98 #io-channel-cells = <1>; 99 }; 100 101 pinctrl: pin-controller@40010800 { 102 reg = <0x40010800 0x2000>; 103 104 gpiof: gpio@40011c00 { 105 compatible = "st,stm32-gpio"; 106 gpio-controller; 107 #gpio-cells = <2>; 108 reg = <0x40011c00 0x400>; 109 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>; 110 }; 111 112 gpiog: gpio@40012000 { 113 compatible = "st,stm32-gpio"; 114 gpio-controller; 115 #gpio-cells = <2>; 116 reg = <0x40012000 0x400>; 117 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; 118 }; 119 }; 120 121 adc2: adc@40012800 { 122 compatible = "st,stm32-adc"; 123 reg = <0x40012800 0x400>; 124 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>; 125 /* Shares vector with ADC1 */ 126 interrupts = <18 0>; 127 status = "disabled"; 128 #io-channel-cells = <1>; 129 }; 130 131 adc3: adc@40013c00 { 132 compatible = "st,stm32-adc"; 133 reg = <0x40013c00 0x400>; 134 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>; 135 interrupts = <47 0>; 136 status = "disabled"; 137 #io-channel-cells = <1>; 138 }; 139 140 timers8: timers@40013400 { 141 compatible = "st,stm32-timers"; 142 reg = <0x40013400 0x400>; 143 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; 144 resets = <&rctl STM32_RESET(APB2, 13U)>; 145 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 146 interrupt-names = "brk", "up", "trgcom", "cc"; 147 st,prescaler = <0>; 148 status = "disabled"; 149 150 pwm { 151 compatible = "st,stm32-pwm"; 152 status = "disabled"; 153 #pwm-cells = <3>; 154 }; 155 }; 156 157 dma2: dma@40020400 { 158 compatible = "st,stm32-dma-v2bis"; 159 #dma-cells = <2>; 160 reg = <0x40020400 0x400>; 161 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; 162 interrupts = < 56 0 57 0 58 0 59 0 60 0>; 163 status = "disabled"; 164 }; 165 }; 166}; 167