1/*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f051.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f071", "st,stm32f0", "simple-bus";
12
13		flash-controller@40022000 {
14			flash0: flash@8000000 {
15				erase-block-size = <2048>;
16			};
17		};
18
19		clocks {
20			clk_hsi48: clk-hsi48 {
21				#clock-cells = <0>;
22				compatible = "fixed-clock";
23				clock-frequency = <DT_FREQ_M(48)>;
24				status = "disabled";
25			};
26		};
27
28		pinctrl: pin-controller@48000000 {
29			gpioe: gpio@48001000 {
30				compatible = "st,stm32-gpio";
31				gpio-controller;
32				#gpio-cells = <2>;
33				reg = <0x48001000 0x400>;
34				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
35			};
36		};
37
38		/*
39		 * USARTs 3-4 share the same IRQ on stm32f071xx devices. This
40		 * configuration is not currently supported, so at most one of
41		 * these may be enabled at a time. Enabling more than one will
42		 * result in a build failure.
43		 */
44		usart3: serial@40004800 {
45			compatible = "st,stm32-usart", "st,stm32-uart";
46			reg = <0x40004800 0x400>;
47			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
48			resets = <&rctl STM32_RESET(APB1, 18U)>;
49			interrupts = <29 0>;
50			status = "disabled";
51		};
52
53		usart4: serial@40004c00 {
54			compatible = "st,stm32-usart", "st,stm32-uart";
55			reg = <0x40004c00 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
57			resets = <&rctl STM32_RESET(APB1, 19U)>;
58			interrupts = <29 0>;
59			status = "disabled";
60		};
61
62		timers7: timers@40001400 {
63			compatible = "st,stm32-timers";
64			reg = <0x40001400 0x400>;
65			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
66			resets = <&rctl STM32_RESET(APB1, 5U)>;
67			interrupts = <18 0>;
68			interrupt-names = "global";
69			st,prescaler = <0>;
70			status = "disabled";
71		};
72
73		dma1: dma@40020000 {
74			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
75		};
76	};
77};
78