1/*
2 * Copyright (c) 2021 Sateesh Kotapati
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <arm/silabs/gpio_gecko.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/i2c/i2c.h>
11#include <dt-bindings/pinctrl/gecko-pinctrl.h>
12#include <dt-bindings/adc/adc.h>
13
14/ {
15	chosen {
16		zephyr,flash-controller = &msc;
17		zephyr,entropy = &trng;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23		cpu0: cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-m33";
26			reg = <0>;
27			/*
28			 * EM1 is enabled by default because it is
29			 * unconditionally safe.
30			 *
31			 * EM2/3 can be enabled by the board code if proper
32			 * timing configuration is ensured:
33			 * - for EM2, EM3: BURTC used as sys_clock
34			 * - for EM3: BURTC clocked from ULFRCO
35			 * Using BURTC as sys_clock instead of SysTick
36			 * has implications on system performance. Read
37			 * KConfig documentation entry before enabling it.
38			 */
39			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
40		};
41
42		power-states {
43			/*
44			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
45			 * enabled.
46			 */
47			pstate_em1: em1 {
48				compatible = "zephyr,power-state";
49				power-state-name = "runtime-idle";
50				min-residency-us = <4>;
51				/* HFXO remains active */
52				exit-latency-us = <2>;
53			};
54
55			/*
56			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
57			 * scaled down, etc.
58			 */
59			pstate_em2: em2 {
60				compatible = "zephyr,power-state";
61				power-state-name = "suspend-to-idle";
62				min-residency-us = <260>;
63				exit-latency-us = <250>;
64			};
65
66			/*
67			 * EM3 seems to be exactly the same as EM2 except that
68			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
69			 * as BURTC clock for the system to not lose track of time and
70			 * wake up.
71			 */
72			pstate_em3: em3 {
73				compatible = "zephyr,power-state";
74				power-state-name = "standby";
75				min-residency-us = <20000>;
76				exit-latency-us = <2000>;
77			};
78		};
79	};
80
81	sram0: memory@20000000 {
82		compatible = "mmio-sram";
83	};
84
85	soc {
86		msc: flash-controller@50030000 {
87			compatible = "silabs,gecko-flash-controller";
88			reg = <0x50030000 0xC69>;
89			interrupts = <49 0>;
90
91			#address-cells = <1>;
92			#size-cells = <1>;
93		};
94
95		usart0: usart@5005c000 {
96			compatible = "silabs,gecko-spi-usart";
97			reg = <0x5005C000 0x400>;
98			interrupt-names = "rx", "tx";
99			#address-cells = <1>;
100			#size-cells = <0>;
101			status = "disabled";
102		};
103
104		usart1: usart@50060000 {
105			compatible = "silabs,gecko-usart";
106			reg = <0x50060000 0x400>;
107			interrupt-names = "rx", "tx";
108			status = "disabled";
109		};
110
111		burtc0: burtc@50064000 {
112			compatible = "silabs,gecko-burtc";
113			reg = <0x50064000 0x3034>;
114			status = "disabled";
115		};
116
117		stimer0: stimer@58000000 {
118			compatible = "silabs,gecko-stimer";
119			reg = <0x58000000 0x3054>;
120			clock-frequency = <32768>;
121			prescaler = <1>;
122			status = "disabled";
123		};
124
125		trng: trng@4c021000 {
126			compatible = "silabs,gecko-trng";
127			reg = <0x4C021000 0x1000>;
128			status = "disabled";
129			interrupts = <0x1 0x0>;
130		};
131
132		i2c0: i2c@5a010000 {
133			compatible = "silabs,gecko-i2c";
134			clock-frequency = <I2C_BITRATE_STANDARD>;
135			reg = <0x5a010000 0x3044>;
136			#address-cells = <1>;
137			#size-cells = <0>;
138			status = "disabled";
139		};
140
141		i2c1: i2c@50068000 {
142			compatible = "silabs,gecko-i2c";
143			clock-frequency = <I2C_BITRATE_STANDARD>;
144			reg = <0x50068000 0x3044>;
145			#address-cells = <1>;
146			#size-cells = <0>;
147			status = "disabled";
148		};
149
150		gpio: gpio@5003c000 {
151			compatible = "silabs,gecko-gpio";
152			reg = <0x5003C000 0x3660>;
153			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
154
155			ranges;
156			#address-cells = <1>;
157			#size-cells = <1>;
158
159			gpioa: gpio@5003c000 {
160				compatible = "silabs,gecko-gpio-port";
161				reg = <0x5003C000 0x30>;
162				gpio-controller;
163				#gpio-cells = <2>;
164				status = "disabled";
165			};
166
167			gpiob: gpio@5003c030 {
168				compatible = "silabs,gecko-gpio-port";
169				reg = <0x5003C030 0x30>;
170				gpio-controller;
171				#gpio-cells = <2>;
172				status = "disabled";
173			};
174
175			gpioc: gpio@5003c060 {
176				compatible = "silabs,gecko-gpio-port";
177				reg = <0x5003C060 0x30>;
178				gpio-controller;
179				#gpio-cells = <2>;
180				status = "disabled";
181			};
182
183			gpiod: gpio@5003c090 {
184				compatible = "silabs,gecko-gpio-port";
185				reg = <0x5003C090 0x30>;
186				gpio-controller;
187				#gpio-cells = <2>;
188				status = "disabled";
189			};
190
191			gpiof: gpio@5003c0c0 {
192				compatible = "silabs,gecko-gpio-port";
193				reg = <0x5003C0C0 0x30>;
194				gpio-controller;
195				#gpio-cells = <2>;
196				status = "disabled";
197			};
198
199		};
200
201		wdog0: wdog@4a018000 {
202			compatible = "silabs,gecko-wdog";
203			reg = <0x4A018000 0x3028>;
204			peripheral-id = <0>;
205			interrupts = <43 0>;
206			status = "disabled";
207		};
208
209		adc0: adc@5a004000 {
210			compatible = "silabs,gecko-iadc";
211			reg = <0x5a004000 0x4000>;
212			interrupts = <48 0>;
213			status = "disabled";
214			#io-channel-cells = <1>;
215		};
216	};
217};
218
219/ {
220	pinctrl: pin-controller {
221		/* Pin controller is a "virtual" device since SiLabs SoCs do pin
222		 * control in a distributed way (GPIO registers and PSEL
223		 * registers on each peripheral).
224		 */
225		compatible = "silabs,gecko-pinctrl";
226	};
227};
228
229&nvic {
230	arm,num-irq-priority-bits = <4>;
231};
232