1/* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-r52"; 19 reg = <0>; 20 }; 21 22 cpu@1 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-r52"; 25 reg = <1>; 26 }; 27 28 cpu@2 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-r52"; 31 reg = <2>; 32 }; 33 34 cpu@3 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-r52"; 37 reg = <3>; 38 }; 39 40 cpu@4 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-r52"; 43 reg = <4>; 44 }; 45 46 cpu@5 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-r52"; 49 reg = <5>; 50 }; 51 52 cpu@6 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-r52"; 55 reg = <6>; 56 }; 57 58 cpu@7 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-r52"; 61 reg = <7>; 62 }; 63 }; 64 65 arch_timer: timer { 66 compatible = "arm,armv8_timer"; 67 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 68 <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 69 <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 70 <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 71 interrupt-parent = <&gic>; 72 }; 73 74 /* Dummy pinctrl node, filled with pin mux options at board level */ 75 pinctrl: pinctrl { 76 compatible = "nxp,s32ze-pinctrl"; 77 status = "okay"; 78 }; 79 80 soc { 81 interrupt-parent = <&gic>; 82 83 clock: clock-controller@40030000 { 84 compatible = "nxp,s32-clock"; 85 reg = <0x40030000 0x10000>, 86 <0x40200000 0x10000>, 87 <0x40210000 0x10000>, 88 <0x40220000 0x10000>, 89 <0x40260000 0x10000>, 90 <0x40270000 0x10000>, 91 <0x40830000 0x10000>, 92 <0x41030000 0x10000>, 93 <0x41830000 0x10000>, 94 <0x42030000 0x10000>, 95 <0x42830000 0x10000>, 96 <0x44030000 0x10000>, 97 <0x440a0000 0x10000>; 98 #clock-cells = <1>; 99 status = "okay"; 100 }; 101 102 gic: interrupt-controller@47800000 { 103 compatible = "arm,gic-v3", "arm,gic"; 104 reg = <0x47800000 0x10000>, 105 <0x47900000 0x80000>; 106 interrupt-controller; 107 #interrupt-cells = <4>; 108 status = "okay"; 109 }; 110 111 sram0: memory@31780000 { 112 compatible = "mmio-sram"; 113 reg = <0x31780000 DT_SIZE_M(1)>; 114 }; 115 116 sram1: memory@35780000 { 117 compatible = "mmio-sram"; 118 reg = <0x35780000 DT_SIZE_M(1)>; 119 }; 120 121 uart0: uart@40170000 { 122 compatible = "nxp,s32-linflexd"; 123 reg = <0x40170000 0x1000>; 124 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 125 status = "disabled"; 126 }; 127 128 uart1: uart@40180000 { 129 compatible = "nxp,s32-linflexd"; 130 reg = <0x40180000 0x1000>; 131 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 132 status = "disabled"; 133 }; 134 135 uart2: uart@40190000 { 136 compatible = "nxp,s32-linflexd"; 137 reg = <0x40190000 0x1000>; 138 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 139 status = "disabled"; 140 }; 141 142 uart3: uart@40970000 { 143 compatible = "nxp,s32-linflexd"; 144 reg = <0x40970000 0x1000>; 145 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 146 status = "disabled"; 147 }; 148 149 uart4: uart@40980000 { 150 compatible = "nxp,s32-linflexd"; 151 reg = <0x40980000 0x1000>; 152 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 153 status = "disabled"; 154 }; 155 156 uart5: uart@40990000 { 157 compatible = "nxp,s32-linflexd"; 158 reg = <0x40990000 0x1000>; 159 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 160 status = "disabled"; 161 }; 162 163 uart6: uart@42170000 { 164 compatible = "nxp,s32-linflexd"; 165 reg = <0x42170000 0x1000>; 166 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 167 status = "disabled"; 168 }; 169 170 uart7: uart@42180000 { 171 compatible = "nxp,s32-linflexd"; 172 reg = <0x42180000 0x1000>; 173 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 174 status = "disabled"; 175 }; 176 177 uart8: uart@42190000 { 178 compatible = "nxp,s32-linflexd"; 179 reg = <0x42190000 0x1000>; 180 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 181 status = "disabled"; 182 }; 183 184 uart9: uart@42980000 { 185 compatible = "nxp,s32-linflexd"; 186 reg = <0x42980000 0x1000>; 187 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 188 status = "disabled"; 189 }; 190 191 uart10: uart@42990000 { 192 compatible = "nxp,s32-linflexd"; 193 reg = <0x42990000 0x1000>; 194 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 195 status = "disabled"; 196 }; 197 198 uart11: uart@429a0000 { 199 compatible = "nxp,s32-linflexd"; 200 reg = <0x429a0000 0x1000>; 201 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 202 status = "disabled"; 203 }; 204 205 uart12: uart@40330000 { 206 compatible = "nxp,s32-linflexd"; 207 reg = <0x40330000 0x1000>; 208 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 209 status = "disabled"; 210 }; 211 212 siul2_0: siul2@40520000 { 213 reg = <0x40520000 0x10000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 217 eirq0: eirq0@40520010 { 218 compatible = "nxp,s32-siul2-eirq"; 219 reg = <0x40520010 0x04>, <0x40520018 0x04>; 220 reg-names = "disr0", "direr0"; 221 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 status = "disabled"; 225 }; 226 227 gpioa: gpio@40521702 { 228 compatible = "nxp,s32-gpio"; 229 reg = <0x40521702 0x02>, <0x40520240 0x40>; 230 reg-names = "pgpdo", "mscr"; 231 interrupt-parent = <&eirq0>; 232 interrupts = <1 1>, <3 0>, <5 2>, <12 3>, 233 <13 4>, <14 5>, <15 6>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 ngpios = <16>; 237 status = "disabled"; 238 }; 239 240 gpiob: gpio@40521700 { 241 compatible = "nxp,s32-gpio"; 242 reg = <0x40521700 0x02>, <0x40520280 0x40>; 243 reg-names = "pgpdo", "mscr"; 244 interrupt-parent = <&eirq0>; 245 interrupts = <0 7>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 ngpios = <15>; 249 status = "disabled"; 250 }; 251 252 gpioo: gpio@40521716 { 253 compatible = "nxp,s32-gpio"; 254 reg = <0x40521716 0x02>, <0x405204c0 0x40>; 255 reg-names = "pgpdo", "mscr"; 256 gpio-controller; 257 #gpio-cells = <2>; 258 ngpios = <14>; 259 gpio-reserved-ranges = <0 10>; 260 status = "disabled"; 261 }; 262 }; 263 264 siul2_1: siul2@40d20000 { 265 reg = <0x40d20000 0x10000>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 269 eirq1: eirq1@40d20010 { 270 compatible = "nxp,s32-siul2-eirq"; 271 reg = <0x40d20010 0x04>, <0x40d20018 0x04>; 272 reg-names = "disr0", "direr0"; 273 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 status = "disabled"; 277 }; 278 279 gpioc: gpio@40d21700 { 280 compatible = "nxp,s32-gpio"; 281 reg = <0x40d21700 0x02>, <0x40d20280 0x40>; 282 reg-names = "pgpdo", "mscr"; 283 interrupt-parent = <&eirq1>; 284 interrupts = <3 0>, <5 1>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 ngpios = <16>; 288 gpio-reserved-ranges = <0 15>; 289 status = "disabled"; 290 }; 291 292 gpiod: gpio@40d21706 { 293 compatible = "nxp,s32-gpio"; 294 reg = <0x40d21706 0x02>, <0x40d202c0 0x40>; 295 reg-names = "pgpdo", "mscr"; 296 gpio-controller; 297 #gpio-cells = <2>; 298 ngpios = <16>; 299 status = "disabled"; 300 }; 301 302 gpioe: gpio@40d21704 { 303 compatible = "nxp,s32-gpio"; 304 reg = <0x40d21704 0x02>, <0x40d20300 0x40>; 305 reg-names = "pgpdo", "mscr"; 306 gpio-controller; 307 #gpio-cells = <2>; 308 ngpios = <16>; 309 status = "disabled"; 310 }; 311 312 gpiof: gpio@40d2170a { 313 compatible = "nxp,s32-gpio"; 314 reg = <0x40d2170a 0x02>, <0x40d20340 0x40>; 315 reg-names = "pgpdo", "mscr"; 316 gpio-controller; 317 #gpio-cells = <2>; 318 ngpios = <16>; 319 status = "disabled"; 320 }; 321 322 gpiog: gpio@40d21708 { 323 compatible = "nxp,s32-gpio"; 324 reg = <0x40d21708 0x02>, <0x40d20380 0x40>; 325 reg-names = "pgpdo", "mscr"; 326 interrupt-parent = <&eirq1>; 327 interrupts = <0 2>, <1 3>, <4 4>, 328 <5 5>, <10 6>, <11 7>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 ngpios = <12>; 332 status = "disabled"; 333 }; 334 }; 335 336 siul2_3: siul2@41d20000 { 337 reg = <0x41d20000 0x10000>; 338 }; 339 340 siul2_4: siul2@42520000 { 341 reg = <0x42520000 0x10000>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 345 eirq4: eirq4@42520010 { 346 compatible = "nxp,s32-siul2-eirq"; 347 reg = <0x42520010 0x04>, <0x42520018 0x04>; 348 reg-names = "disr0", "direr0"; 349 interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 status = "disabled"; 353 }; 354 355 gpioh: gpio@42521708 { 356 compatible = "nxp,s32-gpio"; 357 reg = <0x42521708 0x02>, <0x42520380 0x40>; 358 reg-names = "pgpdo", "mscr"; 359 gpio-controller; 360 #gpio-cells = <2>; 361 ngpios = <16>; 362 gpio-reserved-ranges = <0 12>; 363 status = "disabled"; 364 }; 365 366 gpioi: gpio@4252170e { 367 compatible = "nxp,s32-gpio"; 368 reg = <0x4252170e 0x02>, <0x425203c0 0x40>; 369 reg-names = "pgpdo", "mscr"; 370 interrupt-parent = <&eirq4>; 371 interrupts = <11 0>, <13 1>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 ngpios = <16>; 375 status = "disabled"; 376 }; 377 378 gpioj: gpio@4252170c { 379 compatible = "nxp,s32-gpio"; 380 reg = <0x4252170c 0x02>, <0x42520400 0x40>; 381 reg-names = "pgpdo", "mscr"; 382 interrupt-parent = <&eirq4>; 383 interrupts = <12 2>; 384 gpio-controller; 385 #gpio-cells = <2>; 386 ngpios = <16>; 387 status = "disabled"; 388 }; 389 390 gpiok: gpio@42521712 { 391 compatible = "nxp,s32-gpio"; 392 reg = <0x42521712 0x02>, <0x42520440 0x40>; 393 reg-names = "pgpdo", "mscr"; 394 interrupt-parent = <&eirq4>; 395 interrupts = <4 3>, <6 4>, <9 5>, 396 <11 6>, <13 7>; 397 gpio-controller; 398 #gpio-cells = <2>; 399 ngpios = <16>; 400 status = "disabled"; 401 }; 402 403 gpiol: gpio@42521710 { 404 compatible = "nxp,s32-gpio"; 405 reg = <0x42521710 0x02>, <0x42520480 0x40>; 406 reg-names = "disr0", "direr0"; 407 reg-names = "pgpdo", "mscr"; 408 gpio-controller; 409 #gpio-cells = <2>; 410 ngpios = <2>; 411 status = "disabled"; 412 }; 413 }; 414 415 siul2_5: siul2@42d20000 { 416 reg = <0x42d20000 0x10000>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 420 eirq5: eirq5@42d20010 { 421 compatible = "nxp,s32-siul2-eirq"; 422 reg = <0x42d20010 0x04>, <0x42d20018 0x04>; 423 reg-names = "disr0", "direr0"; 424 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 status = "disabled"; 428 }; 429 430 gpiom: gpio@42d21710 { 431 compatible = "nxp,s32-gpio"; 432 reg = <0x42d21710 0x02>, <0x42d20480 0x40>; 433 reg-names = "pgpdo", "mscr"; 434 interrupt-parent = <&eirq5>; 435 interrupts = <1 0>, <3 1>, <5 2>, <7 3>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 ngpios = <16>; 439 gpio-reserved-ranges = <0 2>; 440 status = "disabled"; 441 }; 442 443 gpion: gpio@42d21716 { 444 compatible = "nxp,s32-gpio"; 445 reg = <0x42d21716 0x02>, <0x42d204c0 0x40>; 446 reg-names = "pgpdo", "mscr"; 447 interrupt-parent = <&eirq5>; 448 interrupts = <0 4>, <2 5>, <5 6>, <6 7>; 449 gpio-controller; 450 #gpio-cells = <2>; 451 ngpios = <10>; 452 status = "disabled"; 453 }; 454 }; 455 456 spi0: spi@40130000 { 457 compatible = "nxp,s32-spi"; 458 reg = <0x40130000 0x10000>; 459 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 460 clocks = <&clock NXP_S32_SPI0_CLK>; 461 num-cs = <5>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 spi1: spi@40140000 { 468 compatible = "nxp,s32-spi"; 469 reg = <0x40140000 0x10000>; 470 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 471 clocks = <&clock NXP_S32_SPI1_CLK>; 472 num-cs = <5>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 spi2: spi@40930000 { 479 compatible = "nxp,s32-spi"; 480 reg = <0x40930000 0x10000>; 481 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 482 clocks = <&clock NXP_S32_SPI2_CLK>; 483 num-cs = <5>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 spi3: spi@40940000 { 490 compatible = "nxp,s32-spi"; 491 reg = <0x40940000 0x10000>; 492 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 493 clocks = <&clock NXP_S32_SPI3_CLK>; 494 num-cs = <5>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 status = "disabled"; 498 }; 499 500 spi4: spi@40950000 { 501 compatible = "nxp,s32-spi"; 502 reg = <0x40950000 0x10000>; 503 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 504 clocks = <&clock NXP_S32_SPI4_CLK>; 505 num-cs = <5>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 spi5: spi@42130000 { 512 compatible = "nxp,s32-spi"; 513 reg = <0x42130000 0x10000>; 514 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 515 clocks = <&clock NXP_S32_SPI5_CLK>; 516 num-cs = <5>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 spi6: spi@42140000 { 523 compatible = "nxp,s32-spi"; 524 reg = <0x42140000 0x10000>; 525 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 526 clocks = <&clock NXP_S32_SPI6_CLK>; 527 num-cs = <5>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 spi7: spi@42150000 { 534 compatible = "nxp,s32-spi"; 535 reg = <0x42150000 0x10000>; 536 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 537 clocks = <&clock NXP_S32_SPI7_CLK>; 538 num-cs = <5>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 spi8: spi@42930000 { 545 compatible = "nxp,s32-spi"; 546 reg = <0x42930000 0x10000>; 547 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 548 clocks = <&clock NXP_S32_SPI8_CLK>; 549 num-cs = <5>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 }; 554 555 spi9: spi@42940000 { 556 compatible = "nxp,s32-spi"; 557 reg = <0x42940000 0x10000>; 558 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 559 clocks = <&clock NXP_S32_SPI9_CLK>; 560 num-cs = <5>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 mru0: mbox@76070000 { 567 compatible = "nxp,s32-mru"; 568 reg = <0x76070000 0x10000>; 569 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 570 #mbox-cells = <1>; 571 status = "disabled"; 572 }; 573 574 mru1: mbox@76090000 { 575 compatible = "nxp,s32-mru"; 576 reg = <0x76090000 0x10000>; 577 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 578 #mbox-cells = <1>; 579 status = "disabled"; 580 }; 581 582 mru2: mbox@76270000 { 583 compatible = "nxp,s32-mru"; 584 reg = <0x76270000 0x10000>; 585 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 586 #mbox-cells = <1>; 587 status = "disabled"; 588 }; 589 590 mru3: mbox@76290000 { 591 compatible = "nxp,s32-mru"; 592 reg = <0x76290000 0x10000>; 593 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 594 #mbox-cells = <1>; 595 status = "disabled"; 596 }; 597 598 mru4: mbox@76870000 { 599 compatible = "nxp,s32-mru"; 600 reg = <0x76870000 0x10000>; 601 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 602 #mbox-cells = <1>; 603 status = "disabled"; 604 }; 605 606 mru5: mbox@76890000 { 607 compatible = "nxp,s32-mru"; 608 reg = <0x76890000 0x10000>; 609 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 610 #mbox-cells = <1>; 611 status = "disabled"; 612 }; 613 614 mru6: mbox@76a70000 { 615 compatible = "nxp,s32-mru"; 616 reg = <0x76a70000 0x10000>; 617 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 618 #mbox-cells = <1>; 619 status = "disabled"; 620 }; 621 622 mru7: mbox@76a90000 { 623 compatible = "nxp,s32-mru"; 624 reg = <0x76a90000 0x10000>; 625 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 626 #mbox-cells = <1>; 627 status = "disabled"; 628 }; 629 630 netc: ethernet@74000000 { 631 reg = <0x74000000 0x1000000>; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges; 635 636 emdio: mdio@74b60000 { 637 compatible = "nxp,s32-netc-emdio"; 638 reg = <0x74b60000 0x1c44>; 639 status = "disabled"; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 }; 643 644 enetc_psi0: ethernet@74b00000 { 645 compatible = "nxp,s32-netc-psi"; 646 reg = <0x74b00000 0x10000>; 647 status = "disabled"; 648 }; 649 650 enetc_vsi1: ethernet@74bc0000 { 651 compatible = "nxp,s32-netc-vsi"; 652 reg = <0x74bc0000 0x10000>; 653 status = "disabled"; 654 }; 655 656 enetc_vsi2: ethernet@74bd0000 { 657 compatible = "nxp,s32-netc-vsi"; 658 reg = <0x74bd0000 0x10000>; 659 status = "disabled"; 660 }; 661 662 enetc_vsi3: ethernet@74be0000 { 663 compatible = "nxp,s32-netc-vsi"; 664 reg = <0x74be0000 0x10000>; 665 status = "disabled"; 666 }; 667 668 enetc_vsi4: ethernet@74bf0000 { 669 compatible = "nxp,s32-netc-vsi"; 670 reg = <0x74bf0000 0x10000>; 671 status = "disabled"; 672 }; 673 674 enetc_vsi5: ethernet@74c00000 { 675 compatible = "nxp,s32-netc-vsi"; 676 reg = <0x74c00000 0x10000>; 677 status = "disabled"; 678 }; 679 680 enetc_vsi6: ethernet@74c10000 { 681 compatible = "nxp,s32-netc-vsi"; 682 reg = <0x74c10000 0x10000>; 683 status = "disabled"; 684 }; 685 686 enetc_vsi7: ethernet@74c20000 { 687 compatible = "nxp,s32-netc-vsi"; 688 reg = <0x74c20000 0x10000>; 689 status = "disabled"; 690 }; 691 }; 692 693 can0: can@4741b000 { 694 compatible = "nxp,s32-canxl"; 695 reg = <0x4741b000 0x4000>, 696 <0x47426000 0x4000>, 697 <0x47424000 0x4000>; 698 reg-names = "sic", "grp_ctrl", "dsc_ctrl"; 699 status = "disabled"; 700 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 701 <GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 702 interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ"; 703 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 704 }; 705 706 can1: can@4751b000 { 707 compatible = "nxp,s32-canxl"; 708 reg = <0x4751b000 0x4000>, 709 <0x47526000 0x4000>, 710 <0x47524000 0x4000>; 711 reg-names = "sic", "grp_ctrl", "dsc_ctrl"; 712 status = "disabled"; 713 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 714 <GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 715 interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ"; 716 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 717 }; 718 }; 719}; 720
