1/*
2 * Copyright 2022-2023, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16
17/ {
18	chosen {
19		zephyr,entropy = &trng;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			compatible = "arm,cortex-m33f";
28			reg = <0>;
29			#address-cells = <1>;
30			#size-cells = <1>;
31			cpu-power-states = <&idle &suspend>;
32
33			mpu: mpu@e000ed90 {
34				compatible = "arm,armv8m-mpu";
35				reg = <0xe000ed90 0x40>;
36				arm,num-mpu-regions = <8>;
37			};
38		};
39
40		power-states {
41			/* This is the setting Sleep Mode */
42			idle: idle {
43				compatible = "zephyr,power-state";
44				power-state-name = "runtime-idle";
45				min-residency-us = <0>;
46				exit-latency-us = <0>;
47			};
48			/* This is the setting for Deep-sleep Mode */
49			suspend: suspend {
50				compatible = "nxp,pdcfg-power", "zephyr,power-state";
51				power-state-name = "suspend-to-idle";
52				min-residency-us = <500>;
53				exit-latency-us = <120>;
54				/*
55				 * These values are written to the PDSLEEPCFG
56				 * registers to keep certain blocks such as
57				 * LPOSC, SRAM's, FlexSPI0 SRAM powered on
58				 * during deep sleep mode.
59				 */
60				deep-sleep-config = <0xC800>,
61							<0x80000004>,
62							<0xFFFFFFFF>,
63							<0>;
64			};
65		};
66	};
67};
68
69&sram {
70	#address-cells = <1>;
71	#size-cells = <1>;
72
73	/* RT5XX SRAM partitions are shared
74	 * between code and data. Boards can
75	 * override the reg properties of either sram0 or sram_code nodes to
76	 * change the balance of SRAM allocation.
77	 *
78	 * Note that the sram code region starts at an offset of 0x1B000,
79	 * as the boot ROM will not load code before 0x1C000. The first
80	 * 0x1000 of the image will contain the boot header.
81	 */
82	sram_code: memory@1b000 {
83		compatible = "mmio-sram";
84		reg = <0x1b000 DT_SIZE_K(1428)>;
85	};
86
87	sram0: memory@20180000 {
88		compatible = "mmio-sram";
89		reg = <0x20180000 DT_SIZE_K(3072)>;
90	};
91
92	sram1: memory@40140000 {
93		compatible =  "zephyr,memory-region", "mmio-sram";
94		reg = <0x40140000 DT_SIZE_K(16)>;
95		zephyr,memory-region = "SRAM1";
96		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
97	};
98};
99
100&systick {
101	/*
102	 * RT500 relies by default on the OS Timer for system clock
103	 * implementation, so the SysTick node is not to be enabled.
104	 */
105	status = "disabled";
106};
107
108&peripheral {
109	#address-cells = <1>;
110	#size-cells = <1>;
111	/*
112	 * Note that the offsets here are relative to the base address
113	 * defined in either nxp_rt5xx_ns.dtsi or nxp_rt5xx.dtsi. The base
114	 * addresses differ between non-secure (0x40000000) and secure
115	 * modes (0x50000000).
116	 */
117
118	clkctl0: clkctl@1000 {
119		compatible = "nxp,lpc-syscon";
120		reg = <0x1000 0x1000>;
121		#clock-cells = <1>;
122	};
123
124	iocon: iocon@4000 {
125		compatible = "nxp,lpc-iocon";
126		reg = <0x4000 0x1000>;
127		pinctrl: pinctrl {
128			compatible = "nxp,rt-iocon-pinctrl";
129		};
130	};
131
132	clkctl1: clkctl@21000 {
133		compatible = "nxp,lpc-syscon";
134		reg = <0x21000 0x1000>;
135		#clock-cells = <1>;
136	};
137
138	uuid: uuid@2f50 {
139		compatible = "nxp,lpc-uid";
140		reg = <0x2f50 0x10>;
141	};
142
143	gpio0: gpio@0 {
144		compatible = "nxp,lpc-gpio";
145		reg = <0x100000 0x1000>;
146		int-source = "pint";
147		gpio-controller;
148		#gpio-cells = <2>;
149		port = <0>;
150	};
151
152	gpio1: gpio@1 {
153		compatible = "nxp,lpc-gpio";
154		reg = <0x100000 0x1000>;
155		int-source = "pint";
156		gpio-controller;
157		#gpio-cells = <2>;
158		port = <1>;
159	};
160
161	gpio2: gpio@2 {
162		compatible = "nxp,lpc-gpio";
163		reg = <0x100000 0x1000>;
164		gpio-controller;
165		#gpio-cells = <2>;
166		port = <2>;
167	};
168
169	gpio3: gpio@3 {
170		compatible = "nxp,lpc-gpio";
171		reg = <0x100000 0x1000>;
172		gpio-controller;
173		#gpio-cells = <2>;
174		port = <3>;
175	};
176
177	gpio4: gpio@4 {
178		compatible = "nxp,lpc-gpio";
179		reg = <0x100000 0x1000>;
180		gpio-controller;
181		#gpio-cells = <2>;
182		port = <4>;
183	};
184
185	gpio5: gpio@5 {
186		compatible = "nxp,lpc-gpio";
187		reg = <0x100000 0x1000>;
188		gpio-controller;
189		#gpio-cells = <2>;
190		port = <5>;
191	};
192
193	gpio6: gpio@6 {
194		compatible = "nxp,lpc-gpio";
195		reg = <0x100000 0x1000>;
196		gpio-controller;
197		#gpio-cells = <2>;
198		port = <6>;
199	};
200
201	pint: pint@25000 {
202		compatible = "nxp,pint";
203		reg = <0x25000 0x1000>;
204		interrupt-controller;
205		#interrupt-cells = <1>;
206		#address-cells = <0>;
207		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
208			<35 2>, <36 2>, <37 2>, <38 2>;
209		num-lines = <8>;
210		num-inputs = <64>;
211	};
212
213	flexcomm0: flexcomm@106000 {
214		compatible = "nxp,lpc-flexcomm";
215		reg = <0x106000 0x1000>;
216		interrupts = <14 0>;
217		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
218		status = "disabled";
219	};
220
221	flexcomm1: flexcomm@107000 {
222		compatible = "nxp,lpc-flexcomm";
223		reg = <0x107000 0x1000>;
224		interrupts = <15 0>;
225		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
226		status = "disabled";
227	};
228
229	flexcomm2: flexcomm@108000 {
230		compatible = "nxp,lpc-flexcomm";
231		reg = <0x108000 0x1000>;
232		interrupts = <16 0>;
233		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
234		status = "disabled";
235	};
236
237	flexcomm3: flexcomm@109000 {
238		compatible = "nxp,lpc-flexcomm";
239		reg = <0x109000 0x1000>;
240		interrupts = <17 0>;
241		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
242		status = "disabled";
243	};
244
245	flexcomm4: flexcomm@122000 {
246		compatible = "nxp,lpc-flexcomm";
247		reg = <0x122000 0x1000>;
248		interrupts = <18 0>;
249		clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>;
250		status = "disabled";
251	};
252
253	flexcomm5: flexcomm@123000 {
254		compatible = "nxp,lpc-flexcomm";
255		reg = <0x123000 0x1000>;
256		interrupts = <19 0>;
257		clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>;
258		status = "disabled";
259	};
260
261	flexcomm6: flexcomm@124000 {
262		compatible = "nxp,lpc-flexcomm";
263		reg = <0x124000 0x1000>;
264		interrupts = <43 0>;
265		clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>;
266		status = "disabled";
267	};
268
269	flexcomm7: flexcomm@125000 {
270		compatible = "nxp,lpc-flexcomm";
271		reg = <0x125000 0x1000>;
272		interrupts = <44 0>;
273		clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>;
274		status = "disabled";
275	};
276
277	pmic_i2c: i2c@127000 {
278		compatible = "nxp,lpc-i2c";
279		reg = <0x127000 0x1000>;
280		interrupts = <21 0>;
281		clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>;
282		status = "disabled";
283	};
284
285	flexcomm8: flexcomm@209000 {
286		compatible = "nxp,lpc-flexcomm";
287		reg = <0x209000 0x1000>;
288		interrupts = <60 0>;
289		clocks = <&clkctl1 MCUX_FLEXCOMM8_CLK>;
290		status = "disabled";
291	};
292
293	flexcomm9: flexcomm@20a000 {
294		compatible = "nxp,lpc-flexcomm";
295		reg = <0x20a000 0x1000>;
296		interrupts = <61 0>;
297		clocks = <&clkctl1 MCUX_FLEXCOMM9_CLK>;
298		status = "disabled";
299	};
300
301	flexcomm10: flexcomm@20b000 {
302		compatible = "nxp,lpc-flexcomm";
303		reg = <0x20b000 0x1000>;
304		interrupts = <62 0>;
305		clocks = <&clkctl1 MCUX_FLEXCOMM10_CLK>;
306		status = "disabled";
307	};
308
309	flexcomm11: flexcomm@20c000 {
310		compatible = "nxp,lpc-flexcomm";
311		reg = <0x20c000 0x1000>;
312		interrupts = <63 0>;
313		clocks = <&clkctl1 MCUX_FLEXCOMM11_CLK>;
314		status = "disabled";
315	};
316
317	flexcomm12: flexcomm@20d000 {
318		compatible = "nxp,lpc-flexcomm";
319		reg = <0x20d000 0x1000>;
320		interrupts = <64 0>;
321		clocks = <&clkctl1 MCUX_FLEXCOMM12_CLK>;
322		status = "disabled";
323	};
324
325	flexcomm13: flexcomm@20e000 {
326		compatible = "nxp,lpc-flexcomm";
327		reg = <0x20e000 0x1000>;
328		interrupts = <65 0>;
329		clocks = <&clkctl1 MCUX_FLEXCOMM13_CLK>;
330		status = "disabled";
331	};
332
333	lcdif: lcdif@210000 {
334		compatible = "nxp,dcnano-lcdif";
335		reg = <0x210000 0x1000>;
336		interrupts = <69 0>;
337		status = "disabled";
338	};
339
340	usbhs: usbhs@144000 {
341		compatible = "nxp,mcux-usbd";
342		reg = <0x144000 0x1000>;
343		interrupts = <50 1>;
344		num-bidir-endpoints = <6>;
345		usb-controller-index = "LpcIp3511Hs0";
346		status = "disabled";
347	};
348
349	hs_lspi: spi@126000 {
350		compatible = "nxp,lpc-spi";
351		reg = <0x126000 0x1000>;
352		interrupts = <20 0>;
353		clocks = <&clkctl1 MCUX_HS_SPI_CLK>;
354		status = "disabled";
355		#address-cells = <1>;
356		#size-cells = <0>;
357	};
358
359	hs_lspi1: spi@128000 {
360		compatible = "nxp,lpc-spi";
361		reg = <0x128000 0x1000>;
362		interrupts = <66 0>;
363		clocks = <&clkctl1 MCUX_HS_SPI1_CLK>;
364		status = "disabled";
365		#address-cells = <1>;
366		#size-cells = <0>;
367	};
368
369	dma0: dma-controller@104000 {
370		compatible = "nxp,lpc-dma";
371		reg = <0x104000 0x1000>;
372		interrupts = <1 0>;
373		dma-channels = <37>;
374		nxp,dma-num-of-otrigs = <4>;
375		nxp,dma-otrig-base-address = <RT595_DMA0_OTRIG_BASE>;
376		nxp,dma-itrig-base-address = <RT595_DMA0_ITRIG_BASE>;
377		status = "disabled";
378		#dma-cells = <1>;
379	};
380
381	dma1: dma-controller@105000 {
382		compatible = "nxp,lpc-dma";
383		reg = <0x105000 0x1000>;
384		interrupts = <54 0>;
385		dma-channels = <37>;
386		nxp,dma-num-of-otrigs = <4>;
387		nxp,dma-otrig-base-address = <RT595_DMA1_OTRIG_BASE>;
388		nxp,dma-itrig-base-address = <RT595_DMA1_ITRIG_BASE>;
389		status = "disabled";
390		#dma-cells = <1>;
391	};
392
393	os_timer: timers@113000 {
394		compatible = "nxp,os-timer";
395		reg = <0x113000 0x1000>;
396		interrupts = <41 0>;
397		status = "disabled";
398	};
399
400	rtc: rtc@30000 {
401		compatible = "nxp,lpc-rtc";
402		reg = <0x30000 0x1000>;
403		interrupts = <32 0>;
404		status = "disabled";
405	};
406
407	trng: random@138000 {
408		compatible = "nxp,kinetis-trng";
409		reg = <0x138000 0x1000>;
410		status = "okay";
411		interrupts = <31 0>;
412	};
413
414	sc_timer: pwm@146000 {
415		compatible = "nxp,sctimer-pwm";
416		reg = <0x146000 0x1000>;
417		interrupts = <12 0>;
418		status = "disabled";
419		prescaler = <8>;
420		#pwm-cells = <3>;
421		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
422	};
423
424	wwdt0: watchdog@e000 {
425		compatible = "nxp,lpc-wwdt";
426		reg = <0xe000 0x1000>;
427		interrupts = <0 0>;
428		status = "disabled";
429		clk-divider = <1>;
430	};
431
432	wwdt1: watchdog@2e000 {
433		compatible = "nxp,lpc-wwdt";
434		reg = <0x2e000 0x1000>;
435		interrupts = <52 0>;
436		status = "disabled";
437		clk-divider = <1>;
438	};
439
440	usdhc0: usdhc@136000 {
441		compatible = "nxp,imx-usdhc";
442		reg = <0x136000 0x1000>;
443		status = "disabled";
444		interrupts = <45 0>;
445		clocks = <&clkctl1 MCUX_USDHC1_CLK>;
446		max-current-330 = <1020>;
447		max-current-180 = <1020>;
448		max-bus-freq = <208000000>;
449		min-bus-freq = <400000>;
450	};
451
452	usdhc1: usdhc@137000 {
453		compatible = "nxp,imx-usdhc";
454		reg = <0x137000 0x1000>;
455		status = "disabled";
456		interrupts = <46 0>;
457		clocks = <&clkctl1 MCUX_USDHC2_CLK>;
458		max-current-330 = <1020>;
459		max-current-180 = <1020>;
460		max-bus-freq = <208000000>;
461		min-bus-freq = <400000>;
462	};
463
464	lpadc0: lpadc@13A0000 {
465		compatible = "nxp,lpc-lpadc";
466		reg = <0x13A000 0x304>;
467		interrupts = <22 0>;
468		status = "disabled";
469		clk-divider = <1>;
470		clk-source = <0>;
471		voltage-ref= <1>;
472		calibration-average = <128>;
473		power-level = <0>;
474		offset-value-a = <10>;
475		offset-value-b = <10>;
476		#io-channel-cells = <1>;
477	};
478
479	smartdma: dma@27020 {
480		compatible = "nxp,smartdma";
481		reg = <0x27020 0x1000>;
482		program-mem = <0x24100000>;
483		interrupts = <73 0>;
484		status = "disabled";
485		#dma-cells = <0>;
486	};
487
488	ctimer0: ctimer@28000 {
489		compatible = "nxp,lpc-ctimer";
490		reg = <0x28000 0x1000>;
491		interrupts = <10 0>;
492		status = "disabled";
493		clk-source = <1>;
494		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
495		mode = <0>;
496		input = <0>;
497		prescale = <0>;
498	};
499
500	ctimer1: ctimer@29000 {
501		compatible = "nxp,lpc-ctimer";
502		reg = <0x29000 0x1000>;
503		interrupts = <11 0>;
504		status = "disabled";
505		clk-source = <1>;
506		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
507		mode = <0>;
508		input = <0>;
509		prescale = <0>;
510	};
511
512	ctimer2: ctimer@2a000 {
513		compatible = "nxp,lpc-ctimer";
514		reg = <0x2a000 0x1000>;
515		interrupts = <39 0>;
516		status = "disabled";
517		clk-source = <1>;
518		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
519		mode = <0>;
520		input = <0>;
521		prescale = <0>;
522	};
523
524	ctimer3: ctimer@2b000 {
525		compatible = "nxp,lpc-ctimer";
526		reg = <0x2b000 0x1000>;
527		interrupts = <13 0>;
528		status = "disabled";
529		clk-source = <1>;
530		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
531		mode = <0>;
532		input = <0>;
533		prescale = <0>;
534	};
535
536	ctimer4: ctimer@2c000 {
537		compatible = "nxp,lpc-ctimer";
538		reg = <0x2c000 0x1000>;
539		interrupts = <40 0>;
540		status = "disabled";
541		clk-source = <1>;
542		clocks = <&clkctl1 MCUX_CTIMER4_CLK>;
543		mode = <0>;
544		input = <0>;
545		prescale = <0>;
546	};
547
548	mipi_dsi: mipi_dsi@31000 {
549		compatible = "nxp,mipi-dsi-2l";
550		#address-cells = <1>;
551		#size-cells = <0>;
552		reg = <0x31000 0x1000>;
553		interrupts = <71 0>;
554		clocks = <&clkctl1 MCUX_MIPI_DSI_DPHY_CLK>,
555			<&clkctl1 MCUX_MIPI_DSI_ESC_CLK>,
556			<&clkctl1 MCUX_LCDIF_PIXEL_CLK>;
557		clock-names = "dphy", "esc", "pixel";
558		status = "disabled";
559	};
560
561	i3c0: i3c@36000 {
562		compatible = "nxp,mcux-i3c";
563		reg = <0x36000 0x1000>;
564		interrupts = <49 0>;
565		clocks = <&clkctl1 MCUX_I3C_CLK>;
566		clk-divider = <2>;
567		clk-divider-slow = <1>;
568		clk-divider-tc = <1>;
569		status = "disabled";
570		#address-cells = <3>;
571		#size-cells = <0>;
572	};
573
574	mbox:mbox@110000 {
575		compatible = "nxp,mbox-imx-mu";
576		reg = <0x110000 0x100>;
577		interrupts = <34 0>;
578		rx-channels = <4>;
579		#mbox-cells = <1>;
580		status = "disabled";
581	};
582};
583
584&flexspi {
585	compatible = "nxp,imx-flexspi";
586	status = "disabled";
587	interrupts = <42 0>;
588	#address-cells = <1>;
589	#size-cells = <0>;
590};
591
592&flexspi2 {
593	compatible = "nxp,imx-flexspi";
594	status = "disabled";
595	interrupts = <42 0>;
596	#address-cells = <1>;
597	#size-cells = <0>;
598};
599
600&nvic {
601	arm,num-irq-priority-bits = <3>;
602};
603