1/*
2 * Copyright (c) 2021, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/pm/imx_spc.h>
15#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
16/ {
17	chosen {
18		zephyr,entropy = &caam;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m7";
28			reg = <0>;
29
30			#address-cells = <1>;
31			#size-cells = <1>;
32			d-cache-line-size = <32>;
33
34			mpu: mpu@e000ed90 {
35				compatible = "arm,armv7m-mpu";
36				reg = <0xe000ed90 0x40>;
37				arm,num-mpu-regions = <16>;
38			};
39		};
40		cpu1: cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-m4f";
43			reg = <1>;
44			d-cache-line-size = <32>;
45
46			#address-cells = <1>;
47			#size-cells = <1>;
48
49			mpu: mpu@e000ed90 {
50				compatible = "arm,armv7m-mpu";
51				reg = <0xe000ed90 0x40>;
52				arm,num-mpu-regions = <16>;
53			};
54		};
55
56		power-states {
57			/*
58			 * Power states are managed with set points (see page 30-35 of RT1170
59			 * datasheet). These set points correspond to various power
60			 * savings, and associated transition (residency) times.
61			 *
62			 * Set points 1 and 10 were chosen as sane defaults to offer
63			 * limited power savings and quick transitions when entering idle for
64			 * short periods, and better power savings with longer transition
65			 * times for long idle periods
66			 */
67			idle: set_point_1_wait {
68				/* idle corresponds to set point 1 (wait) for RT1170 */
69				compatible = "zephyr,power-state";
70				power-state-name="runtime-idle";
71				substate-id = <IMX_SPC_SET_POINT_1_WAIT>;
72				min-residency-us = <100>;
73			};
74
75			suspend: set_point_10_suspend {
76				/*  suspend corresponds to set point 10 for RT1170 */
77				compatible = "zephyr,power-state";
78				power-state-name="suspend-to-idle";
79				substate-id = <IMX_SPC_SET_POINT_10_SUSPEND>;
80				min-residency-us = <5000>;
81				exit-latency-us = <500>;
82			};
83		};
84	};
85
86	xtal: xtal-osc {
87		compatible = "fixed-clock";
88		clock-frequency = <24000000>;
89		#clock-cells = <0>;
90	};
91
92	soc {
93		flexspi: spi@400cc000 {
94			compatible = "nxp,imx-flexspi";
95			reg = <0x400cc000 0x4000>;
96			interrupts = <130 0>;
97			#address-cells = <1>;
98			#size-cells = <0>;
99			status = "disabled";
100		};
101
102		flexspi2: spi@400d0000 {
103			compatible = "nxp,imx-flexspi";
104			reg = <0x400d0000 0x4000>;
105			interrupts = <131 0>;
106			#address-cells = <1>;
107			#size-cells = <0>;
108			status = "disabled";
109		};
110
111		semc: semc0@400d4000 {
112			compatible = "nxp,imx-semc";
113			reg = <0x400d4000 0x4000>;
114			interrupts = <132 0>;
115			#address-cells = <1>;
116			#size-cells = <1>;
117		};
118
119		/* GPT1 is used for the hardware timer, not as a standard counter */
120		gpt_hw_timer: gpt@400ec000 {
121			compatible = "nxp,gpt-hw-timer";
122			reg = <0x400ec000 0x4000>;
123			interrupts = <119 0>;
124			status = "disabled";
125		};
126
127		gpt2: gpt@400f0000 {
128			compatible = "nxp,imx-gpt";
129			reg = <0x400f0000 0x4000>;
130			interrupts = <120 0>;
131			gptfreq = <24000000>;
132			clocks = <&ccm IMX_CCM_GPT_CLK 0x41 0>;
133		};
134
135		gpt3: gpt@400f4000 {
136			compatible = "nxp,imx-gpt";
137			reg = <0x400f4000 0x4000>;
138			interrupts = <121 0>;
139			gptfreq = <24000000>;
140			clocks = <&ccm IMX_CCM_GPT_CLK 0x42 0>;
141		};
142
143		gpt4: gpt@400f8000 {
144			compatible = "nxp,imx-gpt";
145			reg = <0x400f8000 0x4000>;
146			interrupts = <122 0>;
147			gptfreq = <24000000>;
148			clocks = <&ccm IMX_CCM_GPT_CLK 0x43 0>;
149		};
150
151		gpt5: gpt@400fc000 {
152			compatible = "nxp,imx-gpt";
153			reg = <0x400fc000 0x4000>;
154			interrupts = <123 0>;
155			gptfreq = <24000000>;
156			clocks = <&ccm IMX_CCM_GPT_CLK 0x44 0>;
157		};
158
159		gpt6: gpt@40100000 {
160			compatible = "nxp,imx-gpt";
161			reg = <0x40100000 0x4000>;
162			interrupts = <124 0>;
163			gptfreq = <24000000>;
164			clocks = <&ccm IMX_CCM_GPT_CLK 0x45 0>;
165		};
166
167		ccm: ccm@40cc0000 {
168			compatible = "nxp,imx-ccm-rev2";
169			reg = <0x40cc0000 0x4000>;
170
171			#clock-cells = <3>;
172		};
173
174		gpio1: gpio@4012c000 {
175			compatible = "nxp,imx-gpio";
176			reg = <0x4012c000 0x4000>;
177			interrupts = <100 0>, <101 0>;
178			gpio-controller;
179			#gpio-cells = <2>;
180		};
181
182		/*
183		 * Note that CM7 and CM4 cores do not have the same memory addresses
184		 * for GPIO2 and GPIO3, so those peripherals are defined in the SOC
185		 * specific DTS files
186		 */
187
188		gpio4: gpio@40138000 {
189			compatible = "nxp,imx-gpio";
190			reg = <0x40138000 0x4000>;
191			interrupts = <106 0>, <107 0>;
192			gpio-controller;
193			#gpio-cells = <2>;
194		};
195
196		gpio5: gpio@4013c000 {
197			compatible = "nxp,imx-gpio";
198			reg = <0x4013c000 0x4000>;
199			interrupts = <108 0>, <109 0>;
200			gpio-controller;
201			#gpio-cells = <2>;
202		};
203
204		gpio6: gpio@40140000 {
205			compatible = "nxp,imx-gpio";
206			reg = <0x40140000 0x4000>;
207			gpio-controller;
208			#gpio-cells = <2>;
209		};
210
211		gpio7: gpio@40c5c000 {
212			compatible = "nxp,imx-gpio";
213			reg = <0x40c5c000 0x4000>;
214			gpio-controller;
215			#gpio-cells = <2>;
216		};
217
218		gpio8: gpio@40c60000 {
219			compatible = "nxp,imx-gpio";
220			reg = <0x40c60000 0x4000>;
221			gpio-controller;
222			#gpio-cells = <2>;
223		};
224
225		gpio9: gpio@40c64000 {
226			compatible = "nxp,imx-gpio";
227			reg = <0x40c64000 0x4000>;
228			gpio-controller;
229			#gpio-cells = <2>;
230		};
231
232		gpio10: gpio@40c68000 {
233			compatible = "nxp,imx-gpio";
234			reg = <0x40c68000 0x4000>;
235			gpio-controller;
236			#gpio-cells = <2>;
237		};
238
239		gpio11: gpio@40c6c000 {
240			compatible = "nxp,imx-gpio";
241			reg = <0x40c6c000 0x4000>;
242			gpio-controller;
243			#gpio-cells = <2>;
244		};
245
246		gpio12: gpio@40c70000 {
247			compatible = "nxp,imx-gpio";
248			reg = <0x40c70000 0x4000>;
249			gpio-controller;
250			#gpio-cells = <2>;
251		};
252
253		gpio13: gpio@40ca0000 {
254			compatible = "nxp,imx-gpio";
255			reg = <0x40ca0000 0x4000>;
256			interrupts = <93 0>;
257			gpio-controller;
258			#gpio-cells = <2>;
259		};
260
261		lpi2c1: i2c@40104000 {
262			compatible = "nxp,imx-lpi2c";
263			clock-frequency = <I2C_BITRATE_STANDARD>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266			reg = <0x40104000 0x4000>;
267			interrupts = <32 0>;
268			clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
269			status = "disabled";
270		};
271
272		lpi2c2: i2c@40108000 {
273			compatible = "nxp,imx-lpi2c";
274			clock-frequency = <I2C_BITRATE_STANDARD>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			reg = <0x40108000 0x4000>;
278			interrupts = <33 0>;
279			clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
280			status = "disabled";
281		};
282
283		lpi2c3: i2c@4010c000 {
284			compatible = "nxp,imx-lpi2c";
285			clock-frequency = <I2C_BITRATE_STANDARD>;
286			#address-cells = <1>;
287			#size-cells = <0>;
288			reg = <0x4010c000 0x4000>;
289			interrupts = <34 0>;
290			clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
291			status = "disabled";
292		};
293
294		lpi2c4: i2c@40110000 {
295			compatible = "nxp,imx-lpi2c";
296			clock-frequency = <I2C_BITRATE_STANDARD>;
297			#address-cells = <1>;
298			#size-cells = <0>;
299			reg = <0x40110000 0x4000>;
300			interrupts = <35 0>;
301			clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
302			status = "disabled";
303		};
304
305		lpi2c5: i2c@40c34000 {
306			compatible = "nxp,imx-lpi2c";
307			clock-frequency = <I2C_BITRATE_STANDARD>;
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x40c34000 0x4000>;
311			interrupts = <36 0>;
312			clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
313			status = "disabled";
314		};
315
316		lpi2c6: i2c@40c38000 {
317			compatible = "nxp,imx-lpi2c";
318			clock-frequency = <I2C_BITRATE_STANDARD>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			reg = <0x40c38000 0x4000>;
322			interrupts = <37 0>;
323			clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
324			status = "disabled";
325		};
326
327		iomuxc: iomuxc@400e8000 {
328			compatible = "nxp,imx-iomuxc";
329			reg = <0x400e8000 0x4000>;
330			status = "okay";
331			pinctrl: pinctrl {
332				status = "okay";
333				compatible = "nxp,mcux-rt11xx-pinctrl";
334			};
335		};
336
337		iomuxc_lpsr: iomuxc_lpsr@40c08000 {
338			compatible = "nxp,mcux-rt-pinctrl";
339			reg = <0x40c08000 0x4000>;
340			status = "disabled";
341		};
342
343		iomuxc_lpsr_gpr: iomuxc_lpsr_gpr@40c08000 {
344			compatible = "nxp,imx-gpr";
345			reg = <0x40c08000 0x4000>;
346			#pinmux-cells = <2>;
347		};
348
349		lcdif: display-controller@40804000 {
350			compatible = "nxp,imx-elcdif";
351			reg = <0x40804000 0x4000>;
352			interrupts = <54 0>;
353			status = "disabled";
354			nxp,pxp = <&pxp>;
355		};
356
357		mipi_dsi: mipi-dsi@4080c000 {
358			compatible = "nxp,imx-mipi-dsi";
359			#address-cells = <1>;
360			#size-cells = <0>;
361			reg = <0x4080c000 0x200>,
362			      <0x4080c200 0x80>,
363			      <0x4080c280 0x80>,
364			      <0x4080c300 0x200>;
365			interrupts = <59 1>;
366			status = "disabled";
367		};
368
369		lpspi1: spi@40114000 {
370			compatible = "nxp,imx-lpspi";
371			reg = <0x40114000 0x4000>;
372			interrupts = <38 3>;
373			status = "disabled";
374			clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
375			#address-cells = <1>;
376			#size-cells = <0>;
377		};
378
379		lpspi2: spi@40118000 {
380			compatible = "nxp,imx-lpspi";
381			reg = <0x40118000 0x4000>;
382			interrupts = <39 3>;
383			status = "disabled";
384			clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
385			#address-cells = <1>;
386			#size-cells = <0>;
387		};
388
389		lpspi3: spi@4011c000 {
390			compatible = "nxp,imx-lpspi";
391			reg = <0x4011c000 0x4000>;
392			interrupts = <40 3>;
393			status = "disabled";
394			clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
395			#address-cells = <1>;
396			#size-cells = <0>;
397		};
398
399		lpspi4: spi@40120000 {
400			compatible = "nxp,imx-lpspi";
401			reg = <0x40120000 0x4000>;
402			interrupts = <41 3>;
403			status = "disabled";
404			clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
405			#address-cells = <1>;
406			#size-cells = <0>;
407		};
408
409		lpspi5: spi@40c2c000 {
410			compatible = "nxp,imx-lpspi";
411			reg = <0x40c2c000 0x4000>;
412			interrupts = <42 3>;
413			status = "disabled";
414			clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
415			#address-cells = <1>;
416			#size-cells = <0>;
417		};
418
419		lpspi6: spi@40c30000 {
420			compatible = "nxp,imx-lpspi";
421			reg = <0x40c30000 0x4000>;
422			interrupts = <43 3>;
423			status = "disabled";
424			clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
425			#address-cells = <1>;
426			#size-cells = <0>;
427		};
428
429		lpuart1: uart@4007c000 {
430			compatible = "nxp,kinetis-lpuart";
431			reg = <0x4007c000 0x4000>;
432			interrupts = <20 0>;
433			clocks = <&ccm IMX_CCM_LPUART1_CLK 0x7c 24>;
434			status = "disabled";
435		};
436
437		lpuart2: uart@40080000 {
438			compatible = "nxp,kinetis-lpuart";
439			reg = <0x40080000 0x4000>;
440			interrupts = <21 0>;
441			clocks = <&ccm IMX_CCM_LPUART2_CLK 0x68 28>;
442			status = "disabled";
443		};
444
445		lpuart3: uart@40084000 {
446			compatible = "nxp,kinetis-lpuart";
447			reg = <0x40084000 0x4000>;
448			interrupts = <22 0>;
449			clocks = <&ccm IMX_CCM_LPUART3_CLK 0x68 12>;
450			status = "disabled";
451		};
452
453		lpuart4: uart@40088000 {
454			compatible = "nxp,kinetis-lpuart";
455			reg = <0x40088000 0x4000>;
456			interrupts = <23 0>;
457			clocks = <&ccm IMX_CCM_LPUART4_CLK 0x6c 24>;
458			status = "disabled";
459		};
460
461		lpuart5: uart@4008c000 {
462			compatible = "nxp,kinetis-lpuart";
463			reg = <0x4008c000 0x4000>;
464			interrupts = <24 0>;
465			clocks = <&ccm IMX_CCM_LPUART5_CLK 0x74 2>;
466			status = "disabled";
467		};
468
469		lpuart6: uart@40090000 {
470			compatible = "nxp,kinetis-lpuart";
471			reg = <0x40090000 0x4000>;
472			interrupts = <25 0>;
473			clocks = <&ccm IMX_CCM_LPUART6_CLK 0x74 6>;
474			status = "disabled";
475		};
476
477		lpuart7: uart@40094000 {
478			compatible = "nxp,kinetis-lpuart";
479			reg = <0x40094000 0x4000>;
480			interrupts = <26 0>;
481			clocks = <&ccm IMX_CCM_LPUART7_CLK 0x7c 26>;
482			status = "disabled";
483		};
484
485		lpuart8: uart@40098000 {
486			compatible = "nxp,kinetis-lpuart";
487			reg = <0x40098000 0x4000>;
488			interrupts = <27 0>;
489			clocks = <&ccm IMX_CCM_LPUART8_CLK 0x80 14>;
490			status = "disabled";
491		};
492
493		lpuart9: uart@4009c000 {
494			compatible = "nxp,kinetis-lpuart";
495			reg = <0x4009c000 0x4000>;
496			interrupts = <28 0>;
497			clocks = <&ccm IMX_CCM_LPUART9_CLK 0x80 14>;
498			status = "disabled";
499		};
500
501		lpuart10: uart@400a0000 {
502			compatible = "nxp,kinetis-lpuart";
503			reg = <0x400a0000 0x4000>;
504			interrupts = <29 0>;
505			clocks = <&ccm IMX_CCM_LPUART10_CLK 0x80 14>;
506			status = "disabled";
507		};
508
509		lpuart11: uart@40c24000 {
510			compatible = "nxp,kinetis-lpuart";
511			reg = <0x40c24000 0x4000>;
512			interrupts = <30 0>;
513			clocks = <&ccm IMX_CCM_LPUART11_CLK 0x80 14>;
514			status = "disabled";
515		};
516
517		lpuart12: uart@40c28000 {
518			compatible = "nxp,kinetis-lpuart";
519			reg = <0x40c28000 0x4000>;
520			interrupts = <31 0>;
521			clocks = <&ccm IMX_CCM_LPUART12_CLK 0x80 14>;
522			status = "disabled";
523		};
524
525		flexpwm1: flexpwm@4018c000 {
526			compatible = "nxp,flexpwm";
527			reg = <0x4018c000 0x4000>;
528			interrupts = <129 0>;
529
530			flexpwm1_pwm0: flexpwm1_pwm0 {
531				compatible = "nxp,imx-pwm";
532				index = <0>;
533				interrupts = <125 0>;
534				#pwm-cells = <3>;
535				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
536				nxp,prescaler = <128>;
537				status = "disabled";
538			};
539
540			flexpwm1_pwm1: flexpwm1_pwm1 {
541				compatible = "nxp,imx-pwm";
542				index = <1>;
543				interrupts = <126 0>;
544				#pwm-cells = <3>;
545				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
546				nxp,prescaler = <128>;
547				status = "disabled";
548			};
549
550			flexpwm1_pwm2: flexpwm1_pwm2 {
551				compatible = "nxp,imx-pwm";
552				index = <2>;
553				interrupts = <127 0>;
554				#pwm-cells = <3>;
555				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
556				nxp,prescaler = <128>;
557				status = "disabled";
558			};
559
560			flexpwm1_pwm3: flexpwm1_pwm3 {
561				compatible = "nxp,imx-pwm";
562				index = <3>;
563				interrupts = <128 0>;
564				#pwm-cells = <3>;
565				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
566				nxp,prescaler = <128>;
567				status = "disabled";
568			};
569		};
570
571		flexpwm2: flexpwm@40190000 {
572			compatible = "nxp,flexpwm";
573			reg = <0x40190000 0x4000>;
574			interrupts =  <181 0>;
575
576			flexpwm2_pwm0: flexpwm2_pwm0 {
577				compatible = "nxp,imx-pwm";
578				index = <0>;
579				interrupts = <177 0>;
580				#pwm-cells = <3>;
581				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
582				nxp,prescaler = <128>;
583				status = "disabled";
584			};
585
586			flexpwm2_pwm1: flexpwm2_pwm1 {
587				compatible = "nxp,imx-pwm";
588				index = <1>;
589				interrupts = <178 0>;
590				#pwm-cells = <3>;
591				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
592				nxp,prescaler = <128>;
593				status = "disabled";
594			};
595
596			flexpwm2_pwm2: flexpwm2_pwm2 {
597				compatible = "nxp,imx-pwm";
598				index = <2>;
599				interrupts = <179 0>;
600				#pwm-cells = <3>;
601				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
602				nxp,prescaler = <128>;
603				status = "disabled";
604			};
605
606			flexpwm2_pwm3: flexpwm2_pwm3 {
607				compatible = "nxp,imx-pwm";
608				index = <3>;
609				interrupts = <180 0>;
610				#pwm-cells = <3>;
611				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
612				nxp,prescaler = <128>;
613				status = "disabled";
614			};
615		};
616
617		flexpwm3: flexpwm@40194000 {
618			compatible = "nxp,flexpwm";
619			reg = <0x40194000 0x4000>;
620			interrupts =  <186 0>;
621
622			flexpwm3_pwm0: flexpwm3_pwm0 {
623				compatible = "nxp,imx-pwm";
624				index = <0>;
625				interrupts = <182 0>;
626				#pwm-cells = <3>;
627				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
628				nxp,prescaler = <128>;
629				status = "disabled";
630			};
631
632			flexpwm3_pwm1: flexpwm3_pwm1 {
633				compatible = "nxp,imx-pwm";
634				index = <1>;
635				interrupts = <183 0>;
636				#pwm-cells = <3>;
637				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
638				nxp,prescaler = <128>;
639				status = "disabled";
640			};
641
642			flexpwm3_pwm2: flexpwm3_pwm2 {
643				compatible = "nxp,imx-pwm";
644				index = <2>;
645				interrupts = <184 0>;
646				#pwm-cells = <3>;
647				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
648				nxp,prescaler = <128>;
649				status = "disabled";
650			};
651
652			flexpwm3_pwm3: flexpwm3_pwm3 {
653				compatible = "nxp,imx-pwm";
654				index = <3>;
655				interrupts = <185 0>;
656				#pwm-cells = <3>;
657				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
658				nxp,prescaler = <128>;
659				status = "disabled";
660			};
661		};
662
663		flexpwm4: flexpwm@40198000 {
664			compatible = "nxp,flexpwm";
665			reg = <0x40198000 0x4000>;
666			interrupts = <191 0>;
667
668			flexpwm4_pwm0: flexpwm4_pwm0 {
669				compatible = "nxp,imx-pwm";
670				index = <0>;
671				interrupts = <187 0>;
672				#pwm-cells = <3>;
673				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
674				nxp,prescaler = <128>;
675				status = "disabled";
676			};
677
678			flexpwm4_pwm1: flexpwm4_pwm1 {
679				compatible = "nxp,imx-pwm";
680				index = <1>;
681				interrupts = <188 0>;
682				#pwm-cells = <3>;
683				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
684				nxp,prescaler = <128>;
685				status = "disabled";
686			};
687
688			flexpwm4_pwm2: flexpwm4_pwm2 {
689				compatible = "nxp,imx-pwm";
690				index = <2>;
691				interrupts = <189 0>;
692				#pwm-cells = <3>;
693				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
694				nxp,prescaler = <128>;
695				status = "disabled";
696			};
697
698			flexpwm4_pwm3: flexpwm4_pwm3 {
699				compatible = "nxp,imx-pwm";
700				index = <3>;
701				interrupts = <190 0>;
702				#pwm-cells = <3>;
703				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
704				nxp,prescaler = <128>;
705				status = "disabled";
706			};
707		};
708
709		enet: ethernet@40424000 {
710			compatible = "nxp,kinetis-ethernet";
711			reg = <0x40424000 0x628>;
712			interrupts = <137 0>;
713			interrupt-names = "COMMON";
714			status = "disabled";
715			phy-addr = <2>;
716			ptp: ptp {
717				compatible = "nxp,kinetis-ptp";
718				status = "disabled";
719				interrupts = <138 0>;
720				interrupt-names = "IEEE1588_TMR";
721			};
722		};
723
724		/*
725		 * enet1g peripheral to use with kinetis-ethernet (eth_mcux) driver
726		 * just like the enet peripheral (i.e. only 10/100Mbit for now)
727		 */
728		enet1g: ethernet@40420000 {
729			compatible = "nxp,kinetis-ethernet";
730			reg = <0x40420000 0x628>;
731			interrupts = <141 0>;
732			interrupt-names = "COMMON";
733			status = "disabled";
734			phy-addr = <1>;
735			ptp1g: ptp {
736				compatible = "nxp,kinetis-ptp";
737				status = "disabled";
738				interrupts = <142 0>;
739				interrupt-names = "IEEE1588_TMR";
740			};
741		};
742
743		caam: caam@40440000 {
744			compatible = "nxp,imx-caam";
745			reg = <0x40440000 0x81000>;
746			interrupts = <69 0>, <70 0>, <71 0>,
747				     <72 0>,  <73 0>,  <74 0>;
748			status = "okay";
749		};
750
751		usb1: usbd@40430000 {
752			compatible = "nxp,mcux-usbd";
753			reg = <0x40430000 0x200>;
754			interrupts = <136 1>;
755			interrupt-names = "usb_otg";
756			clocks = <&xtal>;
757			num-bidir-endpoints = <8>;
758			usb-controller-index = "Ehci0";
759			status = "disabled";
760		};
761
762		usb2: usbd@4042c000 {
763			compatible = "nxp,mcux-usbd";
764			reg = <0x4042c000 0x200>;
765			interrupts = <135 1>;
766			interrupt-names = "usb_otg";
767			clocks = <&xtal>;
768			num-bidir-endpoints = <8>;
769			usb-controller-index = "Ehci1";
770			status = "disabled";
771		};
772
773		usdhc1: usdhc@40418000 {
774			compatible = "nxp,imx-usdhc";
775			reg = <0x40418000 0x4000>;
776			status = "disabled";
777			interrupts = <133 0>;
778			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
779			max-current-330 = <1020>;
780			max-current-180 = <1020>;
781			max-bus-freq = <208000000>;
782			min-bus-freq = <400000>;
783		};
784
785		usdhc2: usdhc@4041c000 {
786			compatible = "nxp,imx-usdhc";
787			reg = <0x4041c000 0x4000>;
788			status = "disabled";
789			interrupts = <134 0>;
790			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
791			max-current-330 = <1020>;
792			max-current-180 = <1020>;
793			max-bus-freq = <208000000>;
794			min-bus-freq = <400000>;
795		};
796
797		csi: csi@40800000 {
798			compatible = "nxp,imx-csi";
799			reg = <0x40800000 0x4000>;
800			interrupts = <56 1>;
801			status = "disabled";
802		};
803
804		flexcan1: can@400c4000 {
805			compatible = "nxp,flexcan-fd", "nxp,flexcan";
806			reg = <0x400c4000 0x1000>;
807			interrupts = <44 0>, <45 0>;
808			interrupt-names = "common", "error";
809			clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
810			clk-source = <0>;
811			sample-point = <875>;
812			sample-point-data = <875>;
813			status = "disabled";
814		};
815
816		flexcan2: can@400c8000 {
817			compatible = "nxp,flexcan-fd", "nxp,flexcan";
818			reg = <0x400c8000 0x1000>;
819			interrupts = <46 0>, <47 0>;
820			interrupt-names = "common", "error";
821			clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>;
822			clk-source = <0>;
823			sample-point = <875>;
824			sample-point-data = <875>;
825			status = "disabled";
826		};
827
828		flexcan3: can@40c3c000 {
829			compatible = "nxp,flexcan-fd", "nxp,flexcan";
830			reg = <0x40c3c000 0x1000>;
831			interrupts = <48 0>, <49 0>;
832			interrupt-names = "common", "error";
833			clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>;
834			clk-source = <0>;
835			sample-point = <875>;
836			sample-point-data = <875>;
837			status = "disabled";
838		};
839
840		wdog1: wdog@40030000 {
841			compatible = "nxp,imx-wdog";
842			reg = <0x40030000 0xA>;
843			status = "disabled";
844			interrupts = <112 0>;
845		};
846
847		ocram: ocram@20200000 {
848			compatible = "zephyr,memory-region", "mmio-sram";
849			zephyr,memory-region = "OCRAM";
850			reg = <0x20200000 DT_SIZE_K(256)>;
851		};
852
853		ocram1: ocram@20240000 {
854			compatible = "zephyr,memory-region", "mmio-sram";
855			zephyr,memory-region = "OCRAM1";
856			reg = <0x20240000 DT_SIZE_K(512)>;
857		};
858
859		ocram2: ocram@202c0000 {
860			compatible = "zephyr,memory-region", "mmio-sram";
861			zephyr,memory-region = "OCRAM2";
862			reg = <0x202c0000 DT_SIZE_K(512)>;
863		};
864
865		lpadc0: lpadc@40050000 {
866			compatible = "nxp,lpc-lpadc";
867			reg = <0x40050000 0x304>;
868			interrupts = <88 0>;
869			status = "disabled";
870			clk-divider = <8>;
871			clk-source = <0>;
872			voltage-ref= <1>;
873			calibration-average = <128>;
874			power-level = <0>;
875			offset-value-a = <10>;
876			offset-value-b = <10>;
877			#io-channel-cells = <1>;
878		};
879
880		lpadc1: lpadc@40054000 {
881			compatible = "nxp,lpc-lpadc";
882			reg = <0x40054000 0x304>;
883			interrupts = <89 0>;
884			status = "disabled";
885			clk-divider = <8>;
886			clk-source = <0>;
887			voltage-ref= <1>;
888			calibration-average = <128>;
889			power-level = <1>;
890			offset-value-a = <10>;
891			offset-value-b = <10>;
892			#io-channel-cells = <1>;
893		};
894
895		acmp1: cmp@401a4000 {
896			compatible = "nxp,kinetis-acmp";
897			reg = <0x401a4000 0x4000>;
898			interrupts = <157 0>;
899			status = "disabled";
900			#io-channel-cells = <2>;
901		};
902
903		acmp2: cmp@401a8000 {
904			compatible = "nxp,kinetis-acmp";
905			reg = <0x401a8000 0x4000>;
906			interrupts = <158 0>;
907			status = "disabled";
908			#io-channel-cells = <2>;
909		};
910
911		acmp3: cmp@401ac000 {
912			compatible = "nxp,kinetis-acmp";
913			reg = <0x401ac000 0x4000>;
914			interrupts = <159 0>;
915			status = "disabled";
916			#io-channel-cells = <2>;
917		};
918
919		acmp4: cmp@401b0000 {
920			compatible = "nxp,kinetis-acmp";
921			reg = <0x401b0000 0x4000>;
922			interrupts = <160 0>;
923			status = "disabled";
924			#io-channel-cells = <2>;
925		};
926
927		anatop: anatop@40c84000 {
928			compatible = "nxp,imx-anatop";
929			reg = <0x40c84000 0x4000>;
930			#clock-cells = <4>;
931			#pll-clock-cells = <3>;
932		};
933
934		edma0: dma-controller@40070000 {
935			#dma-cells = <2>;
936			compatible = "nxp,mcux-edma";
937			dma-channels = <32>;
938			dma-requests = <208>;
939			nxp,mem2mem;
940			nxp,a_on;
941			reg = <0x40070000 0x4000>,
942				<0x40074000 0x4000>;
943			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
944				status = "disabled";
945			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
946				<4 0>, <5 0>, <6 0>, <7 0>,
947				<8 0>, <9 0>, <10 0>, <11 0>,
948				<12 0>, <13 0>, <14 0>, <15 0>,
949				<16 0>;
950			irq-shared-offset = <16>;
951		};
952
953		edma_lpsr0: dma-controller@40c14000 {
954			#dma-cells = <2>;
955			compatible = "nxp,mcux-edma";
956			dma-channels = <32>;
957			dma-requests = <208>;
958			nxp,mem2mem;
959			nxp,a_on;
960			reg = <0x40c14000 0x4000>,
961				<0x40c18000 0x4000>;
962			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
963			status = "disabled";
964			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
965				<4 0>, <5 0>, <6 0>, <7 0>,
966				<8 0>, <9 0>, <10 0>, <11 0>,
967				<12 0>, <13 0>, <14 0>, <15 0>,
968				<16 0>;
969			irq-shared-offset = <16>;
970		};
971
972		pxp: pxp@40814000 {
973			compatible = "nxp,pxp";
974			reg = <0x40814000 0x4000>;
975			interrupts = <57 0>;
976			status = "disabled";
977			#dma-cells = <0>;
978		};
979
980		iomuxcgpr: iomuxcgpr@400e4000 {
981			compatible = "nxp,imx-gpr";
982			reg = <0x400e4000 0x4000>;
983			#pinmux-cells = <2>;
984		};
985
986		sai1: sai@40404000 {
987			compatible = "nxp,mcux-i2s";
988			#address-cells = <1>;
989			#size-cells = <0>;
990			#pinmux-cells = <2>;
991			reg = <0x40404000 0x4000>;
992			clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>;
993			pre-div = <0>;
994			podf = <4>;
995			pll-clocks = <&anatop 0 0 0>,
996					<&anatop 0 0 30>,
997					<&anatop 0 0 1>,
998					<&anatop 0 0 77>,
999					<&anatop 0 0 100>;
1000			pll-clock-names = "src", "lp", "pd", "num", "den";
1001			pinmuxes = <&iomuxcgpr 0x0 0x100>;
1002			interrupts = <76 0>;
1003			nxp,tx-channel = <1>;
1004			status = "disabled";
1005		};
1006
1007		sai2: sai@40408000 {
1008			compatible = "nxp,mcux-i2s";
1009			#address-cells = <1>;
1010			#size-cells = <0>;
1011			#pinmux-cells = <2>;
1012			reg = <0x40408000 0x4000>;
1013			clocks = <&ccm IMX_CCM_SAI2_CLK 0x2084 4>;
1014			pre-div = <0>;
1015			podf = <63>;
1016			pll-clocks = <&anatop 0 0 0>,
1017					<&anatop 0 0 30>,
1018					<&anatop 0 0 1>,
1019					<&anatop 0 0 77>,
1020					<&anatop 0 0 100>;
1021			pll-clock-names = "src", "lp", "pd", "num", "den";
1022			pinmuxes = <&iomuxcgpr 0x4 0x100>;
1023			interrupts = <77 0>;
1024			nxp,tx-channel = <1>;
1025			status = "disabled";
1026		};
1027
1028		sai3: sai@4040c000 {
1029			compatible = "nxp,mcux-i2s";
1030			#address-cells = <1>;
1031			#size-cells = <0>;
1032			#pinmux-cells = <2>;
1033			reg = <0x4040c000 0x4000>;
1034			clocks = <&ccm IMX_CCM_SAI3_CLK 0x2104 4>;
1035			pre-div = <0>;
1036			podf = <63>;
1037			pll-clocks = <&anatop 0 0 0>,
1038					<&anatop 0 0 30>,
1039					<&anatop 0 0 1>,
1040					<&anatop 0 0 77>,
1041					<&anatop 0 0 100>;
1042			pll-clock-names = "src", "lp", "pd", "num", "den";
1043			pinmuxes = <&iomuxcgpr 0x8 0x100>;
1044			interrupts = <78 0>, <79 0>;
1045			nxp,tx-channel = <1>;
1046			status = "disabled";
1047		};
1048
1049		sai4: sai@40c40000 {
1050			compatible = "nxp,mcux-i2s";
1051			#address-cells = <1>;
1052			#size-cells = <0>;
1053			#pinmux-cells = <2>;
1054			reg = <0x40c40000 0x4000>;
1055			clocks = <&ccm IMX_CCM_SAI4_CLK 0x2184 6>;
1056			pre-div = <0>;
1057			podf = <63>;
1058			pll-clocks = <&anatop 0 0 0>,
1059					<&anatop 0 0 30>,
1060					<&anatop 0 0 1>,
1061					<&anatop 0 0 77>,
1062					<&anatop 0 0 100>;
1063			pll-clock-names = "src", "lp", "pd", "num", "den";
1064			pinmuxes = <&iomuxcgpr 0x8 0x200>;
1065			interrupts = <80 0>, <81 0>;
1066			nxp,tx-channel = <1>;
1067			status = "disabled";
1068		};
1069
1070		src: reset-controller@40c04000 {
1071			compatible = "nxp,imx-src-rev2";
1072			reg = <0x40c04000 0x4000>;
1073			status = "okay";
1074		};
1075
1076
1077		qdec1: qdec@40174000 {
1078			compatible = "nxp,mcux-qdec";
1079			reg = <0x40174000 0x4000>;
1080			interrupts = <165 0>;
1081			status = "disabled";
1082		};
1083
1084		qdec2: qdec@40178000 {
1085			compatible = "nxp,mcux-qdec";
1086			reg = <0x40178000 0x4000>;
1087			interrupts = <166 0>;
1088			status = "disabled";
1089		};
1090
1091		qdec3: qdec@4017c000 {
1092			compatible = "nxp,mcux-qdec";
1093			reg = <0x4017c000 0x4000>;
1094			interrupts = <167 0>;
1095			status = "disabled";
1096		};
1097
1098		qdec4: qdec@40180000 {
1099			compatible = "nxp,mcux-qdec";
1100			reg = <0x40180000 0x4000>;
1101			interrupts = <168 0>;
1102			status = "disabled";
1103		};
1104
1105		xbar1: xbar1@4003c000 {
1106			compatible = "nxp,mcux-xbar";
1107			reg = <0x4003c000 0x4000>;
1108			interrupts = <143 0>, <144 0>;
1109			status = "disabled";
1110		};
1111
1112		xbar2: xbar2@40040000 {
1113			compatible = "nxp,mcux-xbar";
1114			reg = <0x40040000 0x4000>;
1115			status = "disabled";
1116		};
1117
1118		xbar3: xbar3@40044000 {
1119			compatible = "nxp,mcux-xbar";
1120			reg = <0x40044000 0x4000>;
1121			status = "disabled";
1122		};
1123
1124	};
1125};
1126
1127&nvic {
1128	arm,num-irq-priority-bits = <4>;
1129};
1130
1131&systick {
1132	/*
1133	 * RT11xx relies by default on the GPT Timer for system clock
1134	 * implementation, so the SysTick node should not be enabled.
1135	 */
1136	status = "disabled";
1137};
1138