1/*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14
15/ {
16	chosen {
17		zephyr,entropy = &trng;
18		die-temp0 = &tempmon;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m7";
28			d-cache-line-size = <32>;
29			reg = <0>;
30			cpu-power-states = <&idle &suspend>;
31			#address-cells = <1>;
32			#size-cells = <1>;
33
34			mpu: mpu@e000ed90 {
35				compatible = "arm,armv7m-mpu";
36				reg = <0xe000ed90 0x40>;
37				arm,num-mpu-regions = <16>;
38			};
39
40			itm: itm@e0000000 {
41				compatible = "arm,armv7m-itm";
42				reg = <0xe0000000 0x1000>;
43				swo-ref-frequency = <132000000>;
44			};
45		};
46
47		power-states {
48			idle: idle {
49				compatible = "zephyr,power-state";
50				power-state-name = "runtime-idle";
51				exit-latency-us = <4000>;
52				min-residency-us = <5000>;
53			};
54			suspend: suspend {
55				compatible = "zephyr,power-state";
56				power-state-name = "suspend-to-idle";
57				exit-latency-us = <5000>;
58				min-residency-us = <10000>;
59			};
60		};
61	};
62
63	sysclk: system-clock {
64		compatible = "fixed-clock";
65		clock-frequency = <600000000>;
66		#clock-cells = <0>;
67	};
68
69	xtal: clock-xtal {
70		compatible = "fixed-clock";
71		clock-frequency = <24000000>;
72		#clock-cells = <0>;
73	};
74
75	rtc_xtal: clock-rtc-xtal {
76		compatible = "fixed-clock";
77		clock-frequency = <32768>;
78		#clock-cells = <0>;
79	};
80
81	/* USB PLL (selected to be FLEXSPI clock source) will be left unchanged */
82	usbclk: usbpll-clock {
83		compatible = "fixed-clock";
84		clock-frequency = <480000000>;
85		#clock-cells = <0>;
86	};
87
88	soc {
89		flexram: flexram@400b0000 {
90			compatible = "nxp,imx-flexram";
91			reg = <0x400b0000 0x4000>;
92			interrupts = <38 0>;
93
94			#address-cells = <1>;
95			#size-cells = <1>;
96
97			itcm: itcm@0 {
98				compatible = "zephyr,memory-region", "nxp,imx-itcm";
99				reg = <0x00000000 DT_SIZE_K(128)>;
100				zephyr,memory-region = "ITCM";
101			};
102
103			dtcm: dtcm@20000000 {
104				compatible = "zephyr,memory-region", "nxp,imx-dtcm";
105				reg = <0x20000000 DT_SIZE_K(128)>;
106				zephyr,memory-region = "DTCM";
107			};
108
109			ocram: ocram@20200000 {
110				compatible = "zephyr,memory-region", "mmio-sram";
111				reg = <0x20200000 DT_SIZE_K(256)>;
112				zephyr,memory-region = "OCRAM";
113			};
114		};
115
116		flexspi: spi@402a8000 {
117			compatible = "nxp,imx-flexspi";
118			reg = <0x402a8000 0x4000>;
119			interrupts = <108 0>;
120			#address-cells = <1>;
121			#size-cells = <0>;
122			ahb-bufferable;
123			ahb-cacheable;
124			status = "disabled";
125		};
126
127		flexspi2: spi@402a4000 {
128			compatible = "nxp,imx-flexspi";
129			reg = <0x402a4000 0x4000>;
130			interrupts = <107 0>;
131			#address-cells = <1>;
132			#size-cells = <0>;
133			ahb-bufferable;
134			ahb-cacheable;
135			status = "disabled";
136		};
137
138		semc: semc0@402f0000 {
139			compatible = "nxp,imx-semc";
140			reg = <0x402f0000 0x4000>;
141			interrupts = <109 0>;
142			#address-cells = <1>;
143			#size-cells = <1>;
144		};
145
146		/* GPT1 is used for the hardware timer, not as a standard counter */
147		gpt_hw_timer: gpt@401ec000 {
148			compatible = "nxp,gpt-hw-timer";
149			reg = <0x401ec000 0x4000>;
150			interrupts = <100 0>;
151			status = "disabled";
152		};
153
154		gpt2: gpt@401f0000 {
155			compatible = "nxp,imx-gpt";
156			reg = <0x401f0000 0x4000>;
157			interrupts = <101 0>;
158			gptfreq = <25000000>;
159			clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
160		};
161
162		qtmr1: qtmr@401dc000 {
163			compatible = "nxp,imx-qtmr";
164			reg = <0x401dc000 0x7a>;
165			interrupts = <133 0>;
166			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
167			qtmr1_timer0: timer0 {
168				compatible = "nxp,imx-tmr";
169				channel = <0>;
170				status = "disabled";
171			};
172			qtmr1_timer1: timer1 {
173				compatible = "nxp,imx-tmr";
174				channel = <1>;
175				status = "disabled";
176			};
177			qtmr1_timer2: timer2 {
178				compatible = "nxp,imx-tmr";
179				channel = <2>;
180				status = "disabled";
181			};
182			qtmr1_timer3: timer3 {
183				compatible = "nxp,imx-tmr";
184				channel = <3>;
185				status = "disabled";
186			};
187		};
188
189		qtmr2: qtmr@401e0000 {
190			compatible = "nxp,imx-qtmr";
191			reg = <0x401e0000 0x7a>;
192			interrupts = <134 0>;
193			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
194			qtmr2_timer0: timer0 {
195				compatible = "nxp,imx-tmr";
196				channel = <0>;
197				status = "disabled";
198			};
199			qtmr2_timer1: timer1 {
200				compatible = "nxp,imx-tmr";
201				channel = <1>;
202				status = "disabled";
203			};
204			qtmr2_timer2: timer2 {
205				compatible = "nxp,imx-tmr";
206				channel = <2>;
207				status = "disabled";
208			};
209			qtmr2_timer3: timer3 {
210				compatible = "nxp,imx-tmr";
211				channel = <3>;
212				status = "disabled";
213			};
214		};
215
216		qtmr3: qtmr@401e4000 {
217			compatible = "nxp,imx-qtmr";
218			reg = <0x401e4000 0x7a>;
219			interrupts = <135 0>;
220			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
221			qtmr3_timer0: timer0 {
222				compatible = "nxp,imx-tmr";
223				channel = <0>;
224				status = "disabled";
225			};
226			qtmr3_timer1: timer1 {
227				compatible = "nxp,imx-tmr";
228				channel = <1>;
229				status = "disabled";
230			};
231			qtmr3_timer2: timer2 {
232				compatible = "nxp,imx-tmr";
233				channel = <2>;
234				status = "disabled";
235			};
236			qtmr3_timer3: timer3 {
237				compatible = "nxp,imx-tmr";
238				channel = <3>;
239				status = "disabled";
240			};
241		};
242
243		qtmr4: qtmr@401e8000 {
244			compatible = "nxp,imx-qtmr";
245			reg = <0x401e8000 0x7a>;
246			interrupts = <136 0>;
247			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
248			qtmr4_timer0: timer0 {
249				compatible = "nxp,imx-tmr";
250				channel = <0>;
251				status = "disabled";
252			};
253			qtmr4_timer1: timer1 {
254				compatible = "nxp,imx-tmr";
255				channel = <1>;
256				status = "disabled";
257			};
258			qtmr4_timer2: timer2 {
259				compatible = "nxp,imx-tmr";
260				channel = <2>;
261				status = "disabled";
262			};
263			qtmr4_timer3: timer3 {
264				compatible = "nxp,imx-tmr";
265				channel = <3>;
266				status = "disabled";
267			};
268		};
269
270		ccm: ccm@400fc000 {
271			compatible = "nxp,imx-ccm";
272			reg = <0x400fc000 0x4000>;
273			clocks = <&xtal>, <&rtc_xtal>;
274			clock-names = "xtal", "rtc-xtal";
275
276			arm-podf {
277				compatible = "fixed-factor-clock";
278				clock-div = <1>;
279				#clock-cells = <0>;
280			};
281
282			ahb-podf {
283				compatible = "fixed-factor-clock";
284				clock-div = <1>;
285				#clock-cells = <0>;
286			};
287
288			ipg-podf {
289				compatible = "fixed-factor-clock";
290				clock-div = <1>;
291				#clock-cells = <0>;
292			};
293
294			#clock-cells = <3>;
295		};
296
297		snvs: snvs@400d4000 {
298			compatible = "nxp,imx-snvs";
299			reg = <0x400d4000 0x4000>;
300
301			snvs_rtc: rtc {
302				compatible = "nxp,imx-snvs-rtc";
303				interrupts = <46 0>;
304			};
305		};
306
307		gpio1: gpio@401b8000 {
308			compatible = "nxp,imx-gpio";
309			reg = <0x401b8000 0x4000>;
310			interrupts = <80 0>, <81 0>;
311			gpio-controller;
312			#gpio-cells = <2>;
313		};
314
315		gpio2: gpio@401bc000 {
316			compatible = "nxp,imx-gpio";
317			reg = <0x401bc000 0x4000>;
318			interrupts = <82 0>, <83 0>;
319			gpio-controller;
320			#gpio-cells = <2>;
321		};
322
323		gpio3: gpio@401c0000 {
324			compatible = "nxp,imx-gpio";
325			reg = <0x401c0000 0x4000>;
326			interrupts = <84 0>, <85 0>;
327			gpio-controller;
328			#gpio-cells = <2>;
329		};
330
331		gpio4: gpio@401c4000 {
332			compatible = "nxp,imx-gpio";
333			reg = <0x401c4000 0x4000>;
334			interrupts = <86 0>, <87 0>;
335			gpio-controller;
336			#gpio-cells = <2>;
337		};
338
339		gpio5: gpio@400c0000 {
340			compatible = "nxp,imx-gpio";
341			reg = <0x400c0000 0x4000>;
342			interrupts = <88 0>, <89 0>;
343			gpio-controller;
344			#gpio-cells = <2>;
345		};
346		/*
347		 * Note: interrupts for GPIO6-9 are not currently supported
348		 * by the gpio driver.
349		 */
350		gpio6: gpio@42000000 {
351			compatible = "nxp,imx-gpio";
352			reg = <0x42000000 0x4000>;
353			gpio-controller;
354			#gpio-cells = <2>;
355		};
356
357		gpio7: gpio@42004000 {
358			compatible = "nxp,imx-gpio";
359			reg = <0x42004000 0x4000>;
360			gpio-controller;
361			#gpio-cells = <2>;
362		};
363
364		gpio8: gpio@42008000 {
365			compatible = "nxp,imx-gpio";
366			reg = <0x42008000 0x4000>;
367			gpio-controller;
368			#gpio-cells = <2>;
369		};
370
371		gpio9: gpio@4200c000 {
372			compatible = "nxp,imx-gpio";
373			reg = <0x4200c000 0x4000>;
374			gpio-controller;
375			#gpio-cells = <2>;
376		};
377
378		lpi2c1: i2c@403f0000 {
379			compatible = "nxp,imx-lpi2c";
380			clock-frequency = <I2C_BITRATE_STANDARD>;
381			#address-cells = <1>;
382			#size-cells = <0>;
383			reg = <0x403f0000 0x4000>;
384			interrupts = <28 0>;
385			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
386			status = "disabled";
387		};
388
389		lpi2c2: i2c@403f4000 {
390			compatible = "nxp,imx-lpi2c";
391			clock-frequency = <I2C_BITRATE_STANDARD>;
392			#address-cells = <1>;
393			#size-cells = <0>;
394			reg = <0x403f4000 0x4000>;
395			interrupts = <29 0>;
396			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
397			status = "disabled";
398		};
399
400		lpi2c3: i2c@403f8000 {
401			compatible = "nxp,imx-lpi2c";
402			clock-frequency = <I2C_BITRATE_STANDARD>;
403			#address-cells = <1>;
404			#size-cells = <0>;
405			reg = <0x403f8000 0x4000>;
406			interrupts = <30 0>;
407			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
408			status = "disabled";
409		};
410
411		lpi2c4: i2c@403fc000 {
412			compatible = "nxp,imx-lpi2c";
413			clock-frequency = <I2C_BITRATE_STANDARD>;
414			#address-cells = <1>;
415			#size-cells = <0>;
416			reg = <0x403fc000 0x4000>;
417			interrupts = <31 0>;
418			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
419			status = "disabled";
420		};
421
422		iomuxc: iomuxc@401f8000 {
423			compatible = "nxp,imx-iomuxc";
424			reg = <0x401f8000 0x4000>;
425			status = "okay";
426			pinctrl: pinctrl {
427				status = "okay";
428				compatible = "nxp,mcux-rt-pinctrl";
429			};
430		};
431
432		lcdif: display-controller@402b8000 {
433			compatible = "nxp,imx-elcdif";
434			reg = <0x402b8000 0x4000>;
435			interrupts = <42 0>;
436			status = "disabled";
437			nxp,pxp = <&pxp>;
438		};
439
440		lpspi1: spi@40394000 {
441			compatible = "nxp,imx-lpspi";
442			reg = <0x40394000 0x4000>;
443			interrupts = <32 3>;
444			status = "disabled";
445			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
446			#address-cells = <1>;
447			#size-cells = <0>;
448		};
449
450		lpspi2: spi@40398000 {
451			compatible = "nxp,imx-lpspi";
452			reg = <0x40398000 0x4000>;
453			interrupts = <33 3>;
454			status = "disabled";
455			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458		};
459
460		lpspi3: spi@4039c000 {
461			compatible = "nxp,imx-lpspi";
462			reg = <0x4039c000 0x4000>;
463			interrupts = <34 3>;
464			status = "disabled";
465			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
466			#address-cells = <1>;
467			#size-cells = <0>;
468		};
469
470		lpspi4: spi@403a0000 {
471			compatible = "nxp,imx-lpspi";
472			reg = <0x403a0000 0x4000>;
473			interrupts = <35 3>;
474			status = "disabled";
475			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
476			#address-cells = <1>;
477			#size-cells = <0>;
478		};
479
480		lpuart1: uart@40184000 {
481			compatible = "nxp,kinetis-lpuart";
482			reg = <0x40184000 0x4000>;
483			interrupts = <20 0>;
484			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
485			dmas = <&edma0 1 2>, <&edma0 2 3>;
486			dma-names = "tx", "rx";
487			status = "disabled";
488		};
489
490		lpuart2: uart@40188000 {
491			compatible = "nxp,kinetis-lpuart";
492			reg = <0x40188000 0x4000>;
493			interrupts = <21 0>;
494			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
495			dmas = <&edma0 3 66>, <&edma0 4 67>;
496			dma-names = "tx", "rx";
497			status = "disabled";
498		};
499
500		lpuart3: uart@4018c000 {
501			compatible = "nxp,kinetis-lpuart";
502			reg = <0x4018c000 0x4000>;
503			interrupts = <22 0>;
504			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
505			dmas = <&edma0 5 4>, <&edma0 6 5>;
506			dma-names = "tx", "rx";
507			status = "disabled";
508		};
509
510		lpuart4: uart@40190000 {
511			compatible = "nxp,kinetis-lpuart";
512			reg = <0x40190000 0x4000>;
513			interrupts = <23 0>;
514			clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
515			dmas = <&edma0 7 68>, <&edma0 8 69>;
516			dma-names = "tx", "rx";
517			status = "disabled";
518		};
519
520		lpuart5: uart@40194000 {
521			compatible = "nxp,kinetis-lpuart";
522			reg = <0x40194000 0x4000>;
523			interrupts = <24 0>;
524			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
525			dmas = <&edma0 9 6>, <&edma0 10 7>;
526			dma-names = "tx", "rx";
527			status = "disabled";
528		};
529
530		lpuart6: uart@40198000 {
531			compatible = "nxp,kinetis-lpuart";
532			reg = <0x40198000 0x4000>;
533			interrupts = <25 0>;
534			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
535			dmas = <&edma0 11 70>, <&edma0 12 71>;
536			dma-names = "tx", "rx";
537			status = "disabled";
538		};
539
540		lpuart7: uart@4019c000 {
541			compatible = "nxp,kinetis-lpuart";
542			reg = <0x4019c000 0x4000>;
543			interrupts = <26 0>;
544			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
545			dmas = <&edma0 13 8>, <&edma0 14 9>;
546			dma-names = "tx", "rx";
547			status = "disabled";
548		};
549
550		lpuart8: uart@401a0000 {
551			compatible = "nxp,kinetis-lpuart";
552			reg = <0x401a0000 0x4000>;
553			interrupts = <27 0>;
554			clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
555			dmas = <&edma0 15 72>, <&edma0 16 73>;
556			dma-names = "tx", "rx";
557			status = "disabled";
558		};
559
560		adc1: adc@400c4000 {
561			compatible = "nxp,mcux-12b1msps-sar";
562			reg = <0x400C4000 0x1000>;
563			interrupts = <67 0>;
564			clk-divider = <1>;
565			sample-period-mode = <0>;
566			status = "disabled";
567			#io-channel-cells = <1>;
568		};
569
570		adc2: adc@400c8000 {
571			compatible = "nxp,mcux-12b1msps-sar";
572			reg = <0x400C8000 0x1000>;
573			interrupts = <68 0>;
574			clk-divider = <1>;
575			sample-period-mode = <0>;
576			status = "disabled";
577			#io-channel-cells = <1>;
578		};
579
580		flexpwm1: flexpwm@403dc000 {
581			compatible = "nxp,flexpwm";
582			reg = <0x403dc000 0x4000>;
583			interrupts = <106 0>;
584
585			flexpwm1_pwm0: flexpwm1_pwm0 {
586				compatible = "nxp,imx-pwm";
587				index = <0>;
588				interrupts = <102 0>;
589				#pwm-cells = <3>;
590				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
591				nxp,prescaler = <128>;
592				status = "disabled";
593			};
594
595			flexpwm1_pwm1: flexpwm1_pwm1 {
596				compatible = "nxp,imx-pwm";
597				index = <1>;
598				interrupts = <103 0>;
599				#pwm-cells = <3>;
600				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
601				nxp,prescaler = <128>;
602				status = "disabled";
603			};
604
605			flexpwm1_pwm2: flexpwm1_pwm2 {
606				compatible = "nxp,imx-pwm";
607				index = <2>;
608				interrupts = <104 0>;
609				#pwm-cells = <3>;
610				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
611				nxp,prescaler = <128>;
612				status = "disabled";
613			};
614
615			flexpwm1_pwm3: flexpwm1_pwm3 {
616				compatible = "nxp,imx-pwm";
617				index = <3>;
618				interrupts = <105 0>;
619				#pwm-cells = <3>;
620				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
621				nxp,prescaler = <128>;
622				status = "disabled";
623			};
624		};
625
626		flexpwm2: flexpwm@403e0000 {
627			compatible = "nxp,flexpwm";
628			reg = <0x403e0000 0x4000>;
629			interrupts =  <141 0>;
630
631			flexpwm2_pwm0: flexpwm2_pwm0 {
632				compatible = "nxp,imx-pwm";
633				index = <0>;
634				interrupts = <137 0>;
635				#pwm-cells = <3>;
636				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
637				nxp,prescaler = <128>;
638				status = "disabled";
639			};
640
641			flexpwm2_pwm1: flexpwm2_pwm1 {
642				compatible = "nxp,imx-pwm";
643				index = <1>;
644				interrupts = <138 0>;
645				#pwm-cells = <3>;
646				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
647				nxp,prescaler = <128>;
648				status = "disabled";
649			};
650
651			flexpwm2_pwm2: flexpwm2_pwm2 {
652				compatible = "nxp,imx-pwm";
653				index = <2>;
654				interrupts = <139 0>;
655				#pwm-cells = <3>;
656				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
657				nxp,prescaler = <128>;
658				status = "disabled";
659			};
660
661			flexpwm2_pwm3: flexpwm2_pwm3 {
662				compatible = "nxp,imx-pwm";
663				index = <3>;
664				interrupts = <140 0>;
665				#pwm-cells = <3>;
666				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
667				nxp,prescaler = <128>;
668				status = "disabled";
669			};
670		};
671
672		flexpwm3: flexpwm@403e4000 {
673			compatible = "nxp,flexpwm";
674			reg = <0x403e4000 0x4000>;
675			interrupts =  <146 0>;
676
677			flexpwm3_pwm0: flexpwm3_pwm0 {
678				compatible = "nxp,imx-pwm";
679				index = <0>;
680				interrupts = <142 0>;
681				#pwm-cells = <3>;
682				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
683				nxp,prescaler = <128>;
684				status = "disabled";
685			};
686
687			flexpwm3_pwm1: flexpwm3_pwm1 {
688				compatible = "nxp,imx-pwm";
689				index = <1>;
690				interrupts = <143 0>;
691				#pwm-cells = <3>;
692				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
693				nxp,prescaler = <128>;
694				status = "disabled";
695			};
696
697			flexpwm3_pwm2: flexpwm3_pwm2 {
698				compatible = "nxp,imx-pwm";
699				index = <2>;
700				interrupts = <144 0>;
701				#pwm-cells = <3>;
702				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
703				nxp,prescaler = <128>;
704				status = "disabled";
705			};
706
707			flexpwm3_pwm3: flexpwm3_pwm3 {
708				compatible = "nxp,imx-pwm";
709				index = <3>;
710				interrupts = <145 0>;
711				#pwm-cells = <3>;
712				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
713				nxp,prescaler = <128>;
714				status = "disabled";
715			};
716		};
717
718		flexpwm4: flexpwm@403e8000 {
719			compatible = "nxp,flexpwm";
720			reg = <0x403e8000 0x4000>;
721			interrupts = <151 0>;
722
723			flexpwm4_pwm0: flexpwm4_pwm0 {
724				compatible = "nxp,imx-pwm";
725				index = <0>;
726				interrupts = <147 0>;
727				#pwm-cells = <3>;
728				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
729				nxp,prescaler = <128>;
730				status = "disabled";
731			};
732
733			flexpwm4_pwm1: flexpwm4_pwm1 {
734				compatible = "nxp,imx-pwm";
735				index = <1>;
736				interrupts = <148 0>;
737				#pwm-cells = <3>;
738				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
739				nxp,prescaler = <128>;
740				status = "disabled";
741			};
742
743			flexpwm4_pwm2: flexpwm4_pwm2 {
744				compatible = "nxp,imx-pwm";
745				index = <2>;
746				interrupts = <149 0>;
747				#pwm-cells = <3>;
748				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
749				nxp,prescaler = <128>;
750				status = "disabled";
751			};
752
753			flexpwm4_pwm3: flexpwm4_pwm3 {
754				compatible = "nxp,imx-pwm";
755				index = <3>;
756				interrupts = <150 0>;
757				#pwm-cells = <3>;
758				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
759				nxp,prescaler = <128>;
760				status = "disabled";
761			};
762		};
763
764		enet: ethernet@402d8000 {
765			compatible = "nxp,kinetis-ethernet";
766			reg = <0x402D8000 0x628>;
767			interrupts = <114 0>;
768			interrupt-names = "COMMON";
769			status = "disabled";
770			phy-addr = <0>;
771			ptp: ptp {
772				compatible = "nxp,kinetis-ptp";
773				status = "disabled";
774				interrupts = <115 0>;
775				interrupt-names = "IEEE1588_TMR";
776			};
777		};
778
779		src: reset-controller@400f8000 {
780			compatible = "nxp,imx-src";
781			reg = <0x400f8000 0x4000>;
782			status = "okay";
783		};
784
785		trng: random@400cc000 {
786			compatible = "nxp,kinetis-trng";
787			reg = <0x400cc000 0x4000>;
788			status = "okay";
789			interrupts = <53 0>;
790		};
791
792		usb1: usbd@402e0000 {
793			compatible = "nxp,mcux-usbd";
794			reg = <0x402E0000 0x200>;
795			interrupts = <113 1>;
796			interrupt-names = "usb_otg";
797			clocks = <&usbclk>;
798			num-bidir-endpoints = <8>;
799			usb-controller-index = "Ehci0";
800			status = "disabled";
801		};
802
803		usb2: usbd@402e0200 {
804			compatible = "nxp,mcux-usbd";
805			reg = <0x402E0200 0x200>;
806			interrupts = <112 1>;
807			interrupt-names = "usb_otg";
808			clocks = <&usbclk>;
809			num-bidir-endpoints = <8>;
810			usb-controller-index = "Ehci1";
811			status = "disabled";
812		};
813
814		usdhc1: usdhc@402c0000 {
815			compatible = "nxp,imx-usdhc";
816			reg = <0x402c0000 0x4000>;
817			status = "disabled";
818			interrupts = <110 0>;
819			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
820			max-current-330 = <1020>;
821			max-current-180 = <1020>;
822			max-bus-freq = <208000000>;
823			min-bus-freq = <400000>;
824		};
825
826		usdhc2: usdhc@402c4000 {
827			compatible = "nxp,imx-usdhc";
828			reg = <0x402c4000 0x4000>;
829			status = "disabled";
830			interrupts = <111 0>;
831			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
832			max-current-330 = <120>;
833			max-current-180 = <45>;
834			max-bus-freq = <198000000>;
835			min-bus-freq = <400000>;
836		};
837
838		csi: csi@402bc000 {
839			compatible = "nxp,imx-csi";
840			reg = <0x402BC000 0x4000>;
841			interrupts = <43 1>;
842			status = "disabled";
843		};
844
845		edma0: dma-controller@400e8000 {
846			#dma-cells = <2>;
847			compatible = "nxp,mcux-edma";
848			dma-channels = <32>;
849			dma-requests = <128>;
850			nxp,mem2mem;
851			nxp,a_on;
852			reg = <0x400E8000 0x4000>,
853				<0x400EC000 0x4000>;
854			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
855				<4 0>, <5 0>, <6 0>, <7 0>,
856				<8 0>, <9 0>, <10 0>, <11 0>,
857				<12 0>, <13 0>, <14 0>, <15 0>,
858				<16 0>;
859			irq-shared-offset = <16>;
860			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
861			status = "disabled";
862		};
863
864		flexcan1: can@401d0000 {
865			compatible = "nxp,flexcan";
866			reg = <0x401d0000 0x1000>;
867			interrupts = <36 0>;
868			interrupt-names = "common";
869			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
870			clk-source = <2>;
871			sample-point = <875>;
872			status = "disabled";
873		};
874
875		flexcan2: can@401d4000 {
876			compatible = "nxp,flexcan";
877			reg = <0x401d4000 0x1000>;
878			interrupts = <37 0>;
879			interrupt-names = "common";
880			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
881			clk-source = <2>;
882			sample-point = <875>;
883			status = "disabled";
884		};
885
886		flexcan3: can@401d8000 {
887			compatible = "nxp,flexcan-fd", "nxp,flexcan";
888			reg = <0x401d8000 0x1000>;
889			interrupts = <154 0>;
890			interrupt-names = "common";
891			clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
892			clk-source = <2>;
893			sample-point = <875>;
894			sample-point-data = <875>;
895			status = "disabled";
896		};
897
898		wdog0: wdog@400b8000 {
899			compatible = "nxp,imx-wdog";
900			reg = <0x400b8000 0xA>;
901			status = "disabled";
902			interrupts = <92 0>;
903		};
904
905		wdog1: wdog@400d0000 {
906			compatible = "nxp,imx-wdog";
907			reg = <0x400d0000 0xA>;
908			status = "disabled";
909			interrupts = <45 0>;
910		};
911
912		anatop: anatop@400d8000 {
913			compatible = "nxp,imx-anatop";
914			reg = <0x400d8000 0x4000>;
915			#clock-cells = <4>;
916			#pll-clock-cells = <3>;
917		};
918
919		iomuxcgpr: iomuxcgpr@400ac000 {
920			compatible = "nxp,imx-gpr";
921			reg = <0x400AC000 0x4000>;
922			#pinmux-cells = <2>;
923		};
924
925		pxp: pxp@402b4000 {
926			compatible = "nxp,pxp";
927			reg = <0x402b4000 0x4000>;
928			interrupts = <44 0>;
929			status = "disabled";
930			#dma-cells = <0>;
931		};
932
933		sai1: sai@40384000 {
934			compatible = "nxp,mcux-i2s";
935			#address-cells = <1>;
936			#size-cells = <0>;
937			#pinmux-cells = <2>;
938			reg = <0x40384000 0x4000>;
939			clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
940			/* Audio PLL Output Frequency is determined by:
941			 * (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
942			 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
943			 */
944		       pll-clocks = <&anatop 0x70 0xC000 0>,
945				      <&anatop 0x70 0x7F 32>,
946				      <&anatop 0x70 0x180000 1>,
947				      <&anatop 0x80 0x3FFFFFFF 77>,
948				      <&anatop 0x90 0x3FFFFFFF 100>;
949			pll-clock-names = "src", "lp", "pd", "num", "den";
950			/* The maximum input frequency into the SAI mclk input is 300MHz
951			 * Based on this requirement, pre-div must be at least 3
952			 * The pre-div and post-div are one less than the actual divide-by amount.
953			 * A pre-div value of 0x1 results in a pre-divider of
954			 * (1+1) = 2
955			 */
956			pre-div = <0x3>;
957			podf = <0x0F>;
958			pinmuxes = <&iomuxcgpr 0x4 0x80000>;
959			interrupts = <56 0>;
960			dmas = <&edma0 0 19>, <&edma0 0 20>;
961			dma-names = "rx", "tx";
962			/* This translates to SAIChannelMask (fsl_sai.c) and
963			 * cannot be 0
964			 */
965			nxp,tx-channel = <1>;
966			nxp,tx-dma-channel = <0>;
967			nxp,rx-dma-channel = <1>;
968			status = "disabled";
969		};
970
971		sai2: sai@40388000 {
972			compatible = "nxp,mcux-i2s";
973			#address-cells = <1>;
974			#size-cells = <0>;
975			#pinmux-cells = <2>;
976			reg = <0x40388000 0x4000>;
977			clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
978			pre-div = <0>;
979			podf = <63>;
980			pll-clocks = <&anatop 0x70 0xC000 0x0>,
981					<&anatop 0x70 0x7F 32>,
982					<&anatop 0x70 0x180000 1>,
983					<&anatop 0x80 0x3FFFFFFF 77>,
984					<&anatop 0x90 0x3FFFFFFF 100>;
985			pll-clock-names = "src", "lp", "pd", "num", "den";
986			pinmuxes = <&iomuxcgpr 0x4 0x100000>;
987			interrupts = <57 0>;
988			dmas = <&edma0 0 21>, <&edma0 0 22>;
989			dma-names = "rx", "tx";
990			nxp,tx-channel = <0>;
991			nxp,tx-dma-channel = <3>;
992			nxp,rx-dma-channel = <4>;
993			status = "disabled";
994		};
995
996		sai3: sai@4038c000 {
997			compatible = "nxp,mcux-i2s";
998			#address-cells = <1>;
999			#size-cells = <0>;
1000			#pinmux-cells = <2>;
1001			reg = <0x4038C000 0x4000>;
1002			clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
1003			pre-div = <0>;
1004			podf = <63>;
1005			pll-clocks = <&anatop 0x70 0xC000 0>,
1006				   <&anatop 0x70 0x7F 32>,
1007				   <&anatop 0x70 0x180000 1>,
1008				   <&anatop 0x80 0x3FFFFFFF 77>,
1009				   <&anatop 0x90 0x3FFFFFFF 100>;
1010			pll-clock-names = "src", "lp", "pd", "num", "den";
1011			pinmuxes = <&iomuxcgpr 0x4 0x200000>;
1012			interrupts = <58 0>, <59 0>;
1013			dmas = <&edma0 0 83>, <&edma0 0 84>;
1014			dma-names = "rx", "tx";
1015			nxp,tx-channel = <0>;
1016			nxp,tx-dma-channel = <5>;
1017			nxp,rx-dma-channel = <6>;
1018			status = "disabled";
1019		};
1020
1021		qdec1: qdec@403c8000 {
1022			compatible = "nxp,mcux-qdec";
1023			reg = <0x403c8000 0x4000>;
1024			interrupts = <129 0>;
1025			status = "disabled";
1026		};
1027
1028		qdec2: qdec@403cc000 {
1029			compatible = "nxp,mcux-qdec";
1030			reg = <0x403cc000 0x4000>;
1031			interrupts = <130 0>;
1032			status = "disabled";
1033		};
1034
1035		qdec3: qdec@403d0000 {
1036			compatible = "nxp,mcux-qdec";
1037			reg = <0x403d0000 0x4000>;
1038			interrupts = <131 0>;
1039			status = "disabled";
1040		};
1041
1042		qdec4: qdec@403d4000 {
1043			compatible = "nxp,mcux-qdec";
1044			reg = <0x403d4000 0x4000>;
1045			interrupts = <132 0>;
1046			status = "disabled";
1047		};
1048
1049		xbar1: xbar1@403bc000 {
1050			compatible = "nxp,mcux-xbar";
1051			reg = <0x403bc000 0x4000>;
1052			interrupts = <116 0>, <117 0>;
1053			status = "disabled";
1054		};
1055
1056		xbar2: xbar2@403c0000 {
1057			compatible = "nxp,mcux-xbar";
1058			reg = <0x403c0000 0x4000>;
1059			status = "disabled";
1060		};
1061
1062		xbar3: xbar3@403c4000 {
1063			compatible = "nxp,mcux-xbar";
1064			reg = <0x403c4000 0x4000>;
1065			status = "disabled";
1066		};
1067
1068		dcp: dcp@402fc000 {
1069			compatible = "nxp,mcux-dcp";
1070			reg = <0x402fc000 0x4000>;
1071			interrupts = <50 0>, <51 0>;
1072			status = "okay";
1073		};
1074
1075		tempmon: tempmon@400d8000 {
1076			compatible = "nxp,tempmon";
1077			reg = <0x400d8000 0x2a0>;
1078			status = "disabled";
1079		};
1080	};
1081};
1082
1083&nvic {
1084	arm,num-irq-priority-bits = <4>;
1085};
1086
1087&systick {
1088	/*
1089	 * RT10xx relies by default on the GPT Timer for system clock
1090	 * implementation, so the SysTick node should not be enabled.
1091	 */
1092	status = "disabled";
1093};
1094