1/*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <mem.h>
12
13/ {
14	aliases{
15		gpio-0 = &gpio0;
16		gpio-1 = &gpio1;
17		mailbox-0 = &mailbox0;
18	};
19
20	chosen {
21		zephyr,flash-controller = &iap;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			compatible = "arm,cortex-m4f";
30			reg = <0>;
31		};
32
33		cpu1: cpu@1 {
34			compatible = "arm,cortex-m0+";
35			reg = <1>;
36		};
37	};
38
39	soc {
40		syscon: syscon@40000000 {
41			compatible = "nxp,lpc-syscon";
42			reg = <0x40000000 0x4000>;
43			#clock-cells = <1>;
44		};
45
46		/*
47		 * lpc54xxx Memory configurations:
48		 * (note: reference manual says "up to <n>K")
49		 * SRAM0 through SRAM3 will be contiguous
50		 *
51		 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
52		 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
53		 * LPC5411x: RAMX: 32K,  SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
54		 *
55		 * SRAM0-SRAM3 will be contiguous memory when present.
56		 *
57		 * The board level or application level device tree can override the memory sizes
58		 * to allocate memory to the different cores of the dual-core platforms.
59		 */
60		sram0:memory@20000000 {
61			compatible = "mmio-sram";
62			reg = <0x20000000 DT_SIZE_K(64)>;
63		};
64
65		sram1:memory@20010000 {
66			compatible = "zephyr,memory-region", "mmio-sram";
67			reg = <0x20010000 DT_SIZE_K(64)>;
68			zephyr,memory-region = "SRAM1";
69		};
70
71		sram2:memory@20020000 {
72			compatible = "zephyr,memory-region", "mmio-sram";
73			reg = <0x20020000 DT_SIZE_K(32)>;
74			zephyr,memory-region = "SRAM2";
75		};
76
77		/*
78		 * LPC54018: 192K @ 0x04000000
79		 * LPC540xx: 192K @ 0x04000000
80		 * LPC541xx:  32K @ 0x04000000
81		 */
82		sramx:memory@04000000{
83			compatible = "mmio-sram";
84			reg = <0x04000000 DT_SIZE_K(32)>;
85		};
86
87		iap: flash-controller@4009c000 {
88			compatible = "nxp,iap-fmc54";
89			reg = <0x4009c000 0x18>;
90			#address-cells = <1>;
91			#size-cells = <1>;
92			status = "disabled";
93			flash0: flash@0 {
94				compatible = "soc-nv-flash";
95				reg = <0 DT_SIZE_K(256)>;
96				erase-block-size = <256>;
97				write-block-size = <256>;
98			};
99		};
100
101		iocon: iocon@40001000 {
102			compatible = "nxp,lpc-iocon";
103			reg = <0x40001000 0x100>;
104			#address-cells = <1>;
105			#size-cells = <1>;
106			ranges = <0x0 0x40001000 0x100>;
107			pinctrl: pinctrl {
108				compatible = "nxp,lpc-iocon-pinctrl";
109			};
110		};
111
112		gpio0: gpio@0 {
113			compatible = "nxp,lpc-gpio";
114			reg = <0x4008c000 0x2488>;
115			int-source = "pint";
116			gpio-controller;
117			#gpio-cells = <2>;
118			port = <0>;
119		};
120
121		gpio1: gpio@1 {
122			compatible = "nxp,lpc-gpio";
123			reg = <0x4008C000 0x2488>;
124			int-source = "pint";
125			gpio-controller;
126			#gpio-cells = <2>;
127			port = <1>;
128		};
129
130		pint: pint@40004000 {
131			compatible = "nxp,pint";
132			reg = <0x40004000 0x1000>;
133			interrupt-controller;
134			#interrupt-cells = <1>;
135			#address-cells = <0>;
136			interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
137				<32 2>, <33 2>, <34 2>, <35 2>;
138			num-lines = <8>;
139			num-inputs = <64>;
140		};
141
142		mailbox0:mailbox@4008b000 {
143			compatible = "nxp,lpc-mailbox";
144			reg = <0x4008b000 0xEC>;
145			interrupts = <31 0>;
146			status = "disabled";
147		};
148
149		flexcomm0: flexcomm@40086000 {
150			compatible = "nxp,lpc-flexcomm";
151			reg = <0x40086000 0x1000>;
152			interrupts = <14 0>;
153			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
154			status = "disabled";
155		};
156
157		flexcomm1: flexcomm@40087000 {
158			compatible = "nxp,lpc-flexcomm";
159			reg = <0x40087000 0x1000>;
160			interrupts = <15 0>;
161			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
162			status = "disabled";
163		};
164
165		flexcomm2: flexcomm@40088000 {
166			compatible = "nxp,lpc-flexcomm";
167			reg = <0x40088000 0x1000>;
168			interrupts = <16 0>;
169			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
170			status = "disabled";
171		};
172
173		flexcomm3: flexcomm@40089000 {
174			compatible = "nxp,lpc-flexcomm";
175			reg = <0x40089000 0x1000>;
176			interrupts = <17 0>;
177			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
178			status = "disabled";
179		};
180
181		flexcomm4: flexcomm@4008a000 {
182			compatible = "nxp,lpc-flexcomm";
183			reg = <0x4008a000 0x1000>;
184			interrupts = <18 0>;
185			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
186			status = "disabled";
187		};
188
189		flexcomm5: flexcomm@40096000 {
190			compatible = "nxp,lpc-flexcomm";
191			reg = <0x40096000 0x1000>;
192			interrupts = <19 0>;
193			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
194			status = "disabled";
195		};
196
197		flexcomm6: flexcomm@40097000 {
198			compatible = "nxp,lpc-flexcomm";
199			reg = <0x40097000 0x1000>;
200			interrupts = <20 0>;
201			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
202			status = "disabled";
203		};
204
205		flexcomm7: flexcomm@40098000 {
206			compatible = "nxp,lpc-flexcomm";
207			reg = <0x40098000 0x1000>;
208			interrupts = <21 0>;
209			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
210			status = "disabled";
211		};
212	};
213};
214
215&nvic {
216	arm,num-irq-priority-bits = <3>;
217};
218