1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <mem.h>
4#include <arm/armv7-m.dtsi>
5#include <zephyr/dt-bindings/adc/adc.h>
6#include <zephyr/dt-bindings/clock/kinetis_sim.h>
7#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/i2c/i2c.h>
10
11/ {
12	aliases {
13		watchdog0 = &wdog;
14	};
15
16	chosen {
17		zephyr,entropy = &rnga;
18		zephyr,flash-controller = &ftfe;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m4f";
28			reg = <0>;
29		};
30	};
31
32	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
33	 * contiguous block in the memory map, however misaligned accesses
34	 * across the 0x2000_0000 boundary are not supported in the Arm
35	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
36	 * someone to extend sram0 without solving this issue, we define two
37	 * separate memory nodes here and only use the upper one for now. A
38	 * potential solution has been proposed in binutils:
39	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
40	 */
41	sram_l: memory@1fff0000 {
42		compatible = "zephyr,memory-region", "mmio-sram";
43		reg = <0x1fff0000 DT_SIZE_K(64)>;
44		zephyr,memory-region = "SRAML";
45	};
46
47	sram0: memory@20000000 {
48		compatible = "mmio-sram";
49		reg = <0x20000000 DT_SIZE_K(192)>;
50	};
51
52	temp0: temp0 {
53		compatible = "nxp,kinetis-temperature";
54		io-channels = <&adc0 26>, <&adc0 27>;
55		io-channel-names = "SENSOR", "BANDGAP";
56		bandgap-voltage = <1000000>;
57		vtemp25 = <716000>;
58		sensor-slope-cold = <1620>;
59		sensor-slope-hot = <1620>;
60		status = "disabled";
61	};
62
63	temp1: temp1 {
64		compatible = "nxp,kinetis-temperature";
65		io-channels = <&adc1 26>, <&adc1 27>;
66		io-channel-names = "SENSOR", "BANDGAP";
67		bandgap-voltage = <1000000>;
68		vtemp25 = <716000>;
69		sensor-slope-cold = <1620>;
70		sensor-slope-hot = <1620>;
71		status = "disabled";
72	};
73
74
75	/* Dummy pinctrl node, filled with pin mux options at board level */
76	pinctrl: pinctrl {
77		compatible = "nxp,kinetis-pinctrl";
78		status = "okay";
79	};
80
81
82	soc {
83		mpu: mpu@4000d000 {
84			compatible = "nxp,k64f-mpu";
85			reg = <0x4000d000 0x824>;
86
87			status = "disabled";
88		};
89
90		mcg: clock-controller@40064000 {
91			compatible = "nxp,kinetis-mcg";
92			reg = <0x40064000 0xd>;
93			#clock-cells = <1>;
94		};
95
96		osc: clock-controller@40065000 {
97			compatible = "nxp,k64f-osc";
98			reg = <0x40065000 0x4>;
99
100			enable-external-reference;
101		};
102
103		rtc: rtc@4003d000 {
104			compatible = "nxp,kinetis-rtc";
105			reg = <0x4003d000 0x1000>;
106			interrupts = <46 0>, <47 0>;
107			interrupt-names = "alarm", "seconds";
108			clock-frequency = <32768>;
109			prescaler = <32768>;
110		};
111
112		sim: sim@40047000 {
113			compatible = "nxp,kinetis-sim";
114			reg = <0x40047000 0x1060>;
115			#clock-cells = <3>;
116
117			core_clk {
118				compatible = "fixed-factor-clock";
119				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
120				clock-div = <1>;
121				#clock-cells = <0>;
122			};
123
124			bus_clk {
125				compatible = "fixed-factor-clock";
126				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
127				clock-div = <2>;
128				#clock-cells = <0>;
129			};
130
131			flexbus_clk {
132				compatible = "fixed-factor-clock";
133				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
134				clock-div = <3>;
135				#clock-cells = <0>;
136			};
137
138			flash_clk {
139				compatible = "fixed-factor-clock";
140				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
141				clock-div = <5>;
142				#clock-cells = <0>;
143			};
144		};
145
146		ftfe: flash-controller@40020000 {
147			compatible = "nxp,kinetis-ftfe";
148			reg = <0x40020000 0x18>;
149			interrupts = <18 0>, <19 0>;
150			interrupt-names = "command-complete", "read-collision";
151			status = "okay";
152
153			#address-cells = <1>;
154			#size-cells = <1>;
155
156			flash0: flash@0 {
157				compatible = "soc-nv-flash";
158				reg = <0 DT_SIZE_M(1)>;
159				erase-block-size = <4096>;
160				write-block-size = <8>;
161			};
162		};
163
164		i2c0: i2c@40066000 {
165			compatible = "nxp,kinetis-i2c";
166			clock-frequency = <I2C_BITRATE_STANDARD>;
167			#address-cells = <1>;
168			#size-cells = <0>;
169			reg = <0x40066000 0x1000>;
170			interrupts = <24 0>;
171			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
172			status = "disabled";
173		};
174
175		i2c1: i2c@40067000 {
176			compatible = "nxp,kinetis-i2c";
177			clock-frequency = <I2C_BITRATE_STANDARD>;
178			#address-cells = <1>;
179			#size-cells = <0>;
180			reg = <0x40067000 0x1000>;
181			interrupts = <25 0>;
182			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
183			status = "disabled";
184		};
185
186		i2c2: i2c@400e6000 {
187			compatible = "nxp,kinetis-i2c";
188			clock-frequency = <I2C_BITRATE_STANDARD>;
189			#address-cells = <1>;
190			#size-cells = <0>;
191			reg = <0x400e6000 0x1000>;
192			interrupts = <74 0>;
193			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
194			status = "disabled";
195		};
196
197		uart0: uart@4006a000 {
198			compatible = "nxp,kinetis-uart";
199			reg = <0x4006a000 0x1000>;
200			interrupts = <31 0>, <32 0>;
201			interrupt-names = "status", "error";
202			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
203
204			status = "disabled";
205		};
206
207		uart1: uart@4006b000 {
208			compatible = "nxp,kinetis-uart";
209			reg = <0x4006b000 0x1000>;
210			interrupts = <33 0>, <34 0>;
211			interrupt-names = "status", "error";
212			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
213
214			status = "disabled";
215		};
216
217		uart2: uart@4006c000 {
218			compatible = "nxp,kinetis-uart";
219			reg = <0x4006c000 0x1000>;
220			interrupts = <35 0>, <36 0>;
221			interrupt-names = "status", "error";
222			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
223
224			status = "disabled";
225		};
226
227		uart3: uart@4006d000 {
228			compatible = "nxp,kinetis-uart";
229			reg = <0x4006d000 0x1000>;
230			interrupts = <37 0>, <38 0>;
231			interrupt-names = "status", "error";
232			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
233
234			status = "disabled";
235		};
236
237		uart4: uart@400ea000 {
238			compatible = "nxp,kinetis-uart";
239			reg = <0x400ea000 0x1000>;
240			interrupts = <66 0>, <67 0>;
241			interrupt-names = "status", "error";
242			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
243
244			status = "disabled";
245		};
246
247		uart5: uart@400eb000 {
248			compatible = "nxp,kinetis-uart";
249			reg = <0x400eb000 0x1000>;
250			interrupts = <68 0>, <69 0>;
251			interrupt-names = "status", "error";
252			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
253
254			status = "disabled";
255		};
256
257		porta: pinmux@40049000 {
258			compatible = "nxp,kinetis-pinmux";
259			reg = <0x40049000 0xd0>;
260			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
261		};
262
263		portb: pinmux@4004a000 {
264			compatible = "nxp,kinetis-pinmux";
265			reg = <0x4004a000 0xd0>;
266			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
267		};
268
269		portc: pinmux@4004b000 {
270			compatible = "nxp,kinetis-pinmux";
271			reg = <0x4004b000 0xd0>;
272			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
273		};
274
275		portd: pinmux@4004c000 {
276			compatible = "nxp,kinetis-pinmux";
277			reg = <0x4004c000 0xd0>;
278			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
279		};
280
281		porte: pinmux@4004d000 {
282			compatible = "nxp,kinetis-pinmux";
283			reg = <0x4004d000 0xd0>;
284			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
285		};
286
287		gpioa: gpio@400ff000 {
288			compatible = "nxp,kinetis-gpio";
289			status = "disabled";
290			reg = <0x400ff000 0x40>;
291			interrupts = <59 2>;
292			gpio-controller;
293			#gpio-cells = <2>;
294			nxp,kinetis-port = <&porta>;
295		};
296
297		gpiob: gpio@400ff040 {
298			compatible = "nxp,kinetis-gpio";
299			status = "disabled";
300			reg = <0x400ff040 0x40>;
301			interrupts = <60 2>;
302			gpio-controller;
303			#gpio-cells = <2>;
304			nxp,kinetis-port = <&portb>;
305		};
306
307		gpioc: gpio@400ff080 {
308			compatible = "nxp,kinetis-gpio";
309			status = "disabled";
310			reg = <0x400ff080 0x40>;
311			interrupts = <61 2>;
312			gpio-controller;
313			#gpio-cells = <2>;
314			nxp,kinetis-port = <&portc>;
315		};
316
317		gpiod: gpio@400ff0c0 {
318			compatible = "nxp,kinetis-gpio";
319			status = "disabled";
320			reg = <0x400ff0c0 0x40>;
321			interrupts = <62 2>;
322			gpio-controller;
323			#gpio-cells = <2>;
324			nxp,kinetis-port = <&portd>;
325		};
326
327		gpioe: gpio@400ff100 {
328			compatible = "nxp,kinetis-gpio";
329			status = "disabled";
330			reg = <0x400ff100 0x40>;
331			interrupts = <63 2>;
332			gpio-controller;
333			#gpio-cells = <2>;
334			nxp,kinetis-port = <&porte>;
335		};
336
337		spi0: spi@4002c000 {
338			compatible = "nxp,kinetis-dspi";
339			reg = <0x4002c000 0x88>;
340			interrupts = <26 3>;
341			dmas = <&edma0 0 14>, <&edma0 0 15>;
342			dma-names = "rx", "tx";
343			rx-fifo-size = <4>;
344			tx-fifo-size = <4>;
345			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			status = "disabled";
349		};
350
351		spi1: spi@4002d000 {
352			compatible = "nxp,kinetis-dspi";
353			reg = <0x4002d000 0x88>;
354			interrupts = <27 3>;
355			dmas = <&edma0 0 16>, <&edma0 0 16>;
356			dma-names = "rx", "tx";
357			rx-fifo-size = <1>;
358			tx-fifo-size = <1>;
359			nxp,rx-tx-chn-share;
360			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
361			#address-cells = <1>;
362			#size-cells = <0>;
363			status = "disabled";
364		};
365
366		spi2: spi@400ac000 {
367			compatible = "nxp,kinetis-dspi";
368			reg = <0x400ac000 0x88>;
369			interrupts = <65 3>;
370			dmas = <&edma0 0 38>, <&edma0 0 39>;
371			dma-names = "rx", "tx";
372			rx-fifo-size = <1>;
373			tx-fifo-size = <1>;
374			nxp,rx-tx-chn-share;
375			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
376			#address-cells = <1>;
377			#size-cells = <0>;
378			status = "disabled";
379		};
380
381		wdog: watchdog@40052000 {
382			compatible = "nxp,kinetis-wdog";
383			reg = <0x40052000 16>;
384			interrupts = <22 0>;
385			clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
386		};
387
388		ftm0: ftm@40038000{
389			compatible = "nxp,kinetis-ftm";
390			reg = <0x40038000 0x98>;
391			interrupts = <42 0>;
392			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
393			prescaler = <16>;
394			status = "disabled";
395		};
396
397		ftm1: ftm@40039000{
398			compatible = "nxp,kinetis-ftm";
399			reg = <0x40039000 0x98>;
400			interrupts = <43 0>;
401			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
402			prescaler = <16>;
403			status = "disabled";
404		};
405
406		ftm2: ftm@4003a000{
407			compatible = "nxp,kinetis-ftm";
408			reg = <0x4003a000 0x98>;
409			interrupts = <44 0>;
410			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
411			prescaler = <16>;
412			status = "disabled";
413		};
414
415		ftm3: ftm@400b9000{
416			compatible = "nxp,kinetis-ftm";
417			reg = <0x400b9000 0x98>;
418			interrupts = <71 0>;
419			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
420			prescaler = <16>;
421			status = "disabled";
422		};
423
424		adc0: adc@4003b000{
425			compatible = "nxp,kinetis-adc16";
426			reg = <0x4003b000 0x70>;
427			clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
428				<&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
429			dmas = <&edma0 0 40>;
430			dma-names = "adc0";
431			clk-source = <0>;
432			interrupts = <39 0>;
433			status = "disabled";
434			#io-channel-cells = <1>;
435		};
436
437		adc1: adc@400bb000{
438			compatible = "nxp,kinetis-adc16";
439			reg = <0x400bb000 0x70>;
440			clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
441				<&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
442			dmas = <&edma0 0 41>;
443			dma-names = "adc1";
444			clk-source = <0>;
445			interrupts = <73 0>;
446			status = "disabled";
447			#io-channel-cells = <1>;
448		};
449
450		dac0: dac@400cc000 {
451			compatible = "nxp,kinetis-dac";
452			reg = <0x400cc000 0x1000>;
453			interrupts = <56 0>;
454			voltage-reference = <1>;
455			status = "disabled";
456			#io-channel-cells = <1>;
457		};
458
459		dac1: dac@400cd000 {
460			compatible = "nxp,kinetis-dac";
461			reg = <0x400cd000 0x1000>;
462			interrupts = <72 0>;
463			voltage-reference = <1>;
464			status = "disabled";
465			#io-channel-cells = <1>;
466		};
467
468		usbotg: usbd@40072000 {
469			compatible = "nxp,kinetis-usbd";
470			reg = <0x40072000 0x1000>;
471			interrupts = <53 1>;
472			interrupt-names = "usb_otg";
473			num-bidir-endpoints = <16>;
474			status = "disabled";
475		};
476
477		enet: ethernet@400c0000 {
478			compatible = "nxp,kinetis-ethernet";
479			reg = <0x400c0000 0x620>;
480			interrupts = <83 0>, <84 0>, <85 0>;
481			interrupt-names = "TX", "RX", "ERR";
482			status = "disabled";
483			phy-addr = <0>;
484			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0 0>;
485			ptp: ptp {
486				compatible = "nxp,kinetis-ptp";
487				status = "disabled";
488				interrupts = <82 0>;
489				interrupt-names = "IEEE1588_TMR";
490			};
491		};
492
493		rnga: random@40029000 {
494			compatible = "nxp,kinetis-rnga";
495			reg = <0x40029000 0x1000>;
496			status = "okay";
497			interrupts = <23 0>;
498		};
499
500		flexcan0: can@40024000 {
501			compatible = "nxp,flexcan";
502			reg = <0x40024000 0x1000>;
503			interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
504			interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
505			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
506			clk-source = <1>;
507			sample-point = <875>;
508			status = "disabled";
509		};
510
511		edma0: dma-controller@40008000 {
512			#dma-cells = <2>;
513			compatible = "nxp,mcux-edma";
514			dma-channels = <16>;
515			dma-requests = <64>;
516			nxp,mem2mem;
517			reg = <0x40008000 0x1000>,
518				<0x40021000 0x1000>;
519			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
520				<4 0>, <5 0>, <6 0>, <7 0>,
521				<8 0>, <9 0>, <10 0>, <11 0>,
522				<12 0>, <13 0>, <14 0>, <15 0>,
523				<16 0>;
524			clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
525				<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
526			status = "disabled";
527		};
528
529		pit0: pit@40037000 {
530			compatible = "nxp,kinetis-pit";
531			reg = <0x40037000 0x1000>;
532			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
533			interrupts = <48 0>, <49 0>, <50 0>, <51 0>;
534			status = "disabled";
535			pit-channel = <0>;
536			pit-period = <1000000>;
537			max-load-value = <0xffffffff>;
538		};
539	};
540};
541
542&nvic {
543	arm,num-irq-priority-bits = <4>;
544};
545