1/*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/rdc/imx_rdc.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m4";
21			reg = <0>;
22		};
23	};
24
25	soc {
26
27		ddr_code: code@10000000 {
28			compatible = "nxp,imx-code-bus";
29			reg = <0x10000000 0xfff0000>;
30		};
31
32		ddr_sys: memory@80000000 {
33			device_type = "memory";
34			compatible = "nxp,imx-sys-bus";
35			reg = <0x80000000 0x60000000>;
36		};
37
38		tcml_code: code@1fff8000 {
39			compatible = "nxp,imx-itcm";
40			reg = <0x1fff8000 DT_SIZE_K(32)>;
41		};
42
43		tcmu_sys: memory@20000000 {
44			compatible = "nxp,imx-dtcm";
45			reg = <0x20000000 DT_SIZE_K(32)>;
46		};
47
48		ocram_code: code@900000 {
49			compatible = "nxp,imx-code-bus";
50			reg = <0x00900000 DT_SIZE_K(128)>;
51		};
52
53		ocram_sys: memory@20200000 {
54			device_type = "memory";
55			compatible = "nxp,imx-sys-bus";
56			reg = <0x20200000 DT_SIZE_K(128)>;
57		};
58
59		ocram_s_code: code@20180000 {
60			compatible = "nxp,imx-code-bus";
61			reg = <0x20180000 DT_SIZE_K(32)>;
62		};
63
64		ocram_s_sys: memory@180000 {
65			device_type = "memory";
66			compatible = "nxp,imx-sys-bus";
67			reg = <0x00180000 DT_SIZE_K(32)>;
68		};
69
70		gpio1: gpio@30200000 {
71			compatible = "nxp,imx-gpio";
72			reg = <0x30200000 0x10000>;
73			interrupts = <64 0>, <65 0>;
74			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
75					       RDC_DOMAIN_PERM_RW)|\
76			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
77					       RDC_DOMAIN_PERM_RW))>;
78			gpio-controller;
79			#gpio-cells = <2>;
80			status = "disabled";
81		};
82
83		gpio2: gpio@30210000 {
84			compatible = "nxp,imx-gpio";
85			reg = <0x30210000 0x10000>;
86			interrupts = <66 0>, <67 0>;
87			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
88					       RDC_DOMAIN_PERM_RW)|\
89			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
90					       RDC_DOMAIN_PERM_RW))>;
91			gpio-controller;
92			#gpio-cells = <2>;
93			status = "disabled";
94		};
95
96		gpio3: gpio@30220000 {
97			compatible = "nxp,imx-gpio";
98			reg = <0x30220000 0x10000>;
99			interrupts = <68 0>, <69 0>;
100			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
101					       RDC_DOMAIN_PERM_RW)|\
102			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
103					       RDC_DOMAIN_PERM_RW))>;
104			gpio-controller;
105			#gpio-cells = <2>;
106			status = "disabled";
107		};
108
109		gpio4: gpio@30230000 {
110			compatible = "nxp,imx-gpio";
111			reg = <0x30230000 0x10000>;
112			interrupts = <70 0>, <71 0>;
113			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
114					       RDC_DOMAIN_PERM_RW)|\
115			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
116					       RDC_DOMAIN_PERM_RW))>;
117			gpio-controller;
118			#gpio-cells = <2>;
119			status = "disabled";
120		};
121
122		gpio5: gpio@30240000 {
123			compatible = "nxp,imx-gpio";
124			reg = <0x30240000 0x10000>;
125			interrupts = <72 0>, <73 0>;
126			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
127					       RDC_DOMAIN_PERM_RW)|\
128			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
129					       RDC_DOMAIN_PERM_RW))>;
130			gpio-controller;
131			#gpio-cells = <2>;
132			status = "disabled";
133		};
134
135		gpio6: gpio@30250000 {
136			compatible = "nxp,imx-gpio";
137			reg = <0x30250000 0x10000>;
138			interrupts = <74 0>, <75 0>;
139			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
140					       RDC_DOMAIN_PERM_RW)|\
141			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
142					       RDC_DOMAIN_PERM_RW))>;
143			gpio-controller;
144			#gpio-cells = <2>;
145			status = "disabled";
146		};
147
148		gpio7: gpio@30260000 {
149			compatible = "nxp,imx-gpio";
150			reg = <0x30260000 0x10000>;
151			interrupts = <76 0>, <77 0>;
152			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
153					       RDC_DOMAIN_PERM_RW)|\
154			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
155					       RDC_DOMAIN_PERM_RW))>;
156			gpio-controller;
157			#gpio-cells = <2>;
158			status = "disabled";
159		};
160
161		/* For now only uart2 is supported and
162		 * tested with the serial driver
163		 */
164		uart1: uart@30860000 {
165			compatible = "nxp,imx-uart";
166			reg = <0x30860000 0x10000>;
167			interrupts = <26 3>;
168			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
169					       RDC_DOMAIN_PERM_RW)|\
170			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
171					       RDC_DOMAIN_PERM_RW))>;
172			status = "disabled";
173		};
174
175		uart2: uart@30890000 {
176			compatible = "nxp,imx-uart";
177			reg = <0x30890000 0x10000>;
178			interrupts = <27 3>;
179			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
180					       RDC_DOMAIN_PERM_RW)|\
181			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
182					       RDC_DOMAIN_PERM_RW))>;
183			status = "disabled";
184		};
185
186		uart3: uart@30880000 {
187			compatible = "nxp,imx-uart";
188			reg = <0x30880000 0x10000>;
189			interrupts = <28 3>;
190			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
191					       RDC_DOMAIN_PERM_RW)|\
192			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
193					       RDC_DOMAIN_PERM_RW))>;
194			status = "disabled";
195		};
196
197		uart4: uart@30a60000 {
198			compatible = "nxp,imx-uart";
199			reg = <0x30a60000 0x10000>;
200			interrupts = <29 3>;
201			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
202					       RDC_DOMAIN_PERM_RW)|\
203			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
204					       RDC_DOMAIN_PERM_RW))>;
205			status = "disabled";
206		};
207
208		uart5: uart@30a70000 {
209			compatible = "nxp,imx-uart";
210			reg = <0x30a70000 0x10000>;
211			interrupts = <30 3>;
212			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
213					       RDC_DOMAIN_PERM_RW)|\
214			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
215					       RDC_DOMAIN_PERM_RW))>;
216			status = "disabled";
217		};
218
219		uart6: uart@30a80000 {
220			compatible = "nxp,imx-uart";
221			reg = <0x30a80000 0x10000>;
222			interrupts = <16 3>;
223			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
224					       RDC_DOMAIN_PERM_RW)|\
225			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
226					       RDC_DOMAIN_PERM_RW))>;
227			status = "disabled";
228		};
229
230		uart7: uart@30a90000 {
231			compatible = "nxp,imx-uart";
232			reg = <0x30a90000 0x10000>;
233			interrupts = <126 3>;
234			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
235					       RDC_DOMAIN_PERM_RW)|\
236			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
237					       RDC_DOMAIN_PERM_RW))>;
238			status = "disabled";
239		};
240
241		mub:mu@30ab0000 {
242			compatible = "nxp,imx-mu";
243			reg = <0x30ab0000 0x4000>;
244			interrupts = <97 0>;
245			rdc = <RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
246					       RDC_DOMAIN_PERM_RW)>;
247			status = "disabled";
248		};
249
250		iomuxc: iomuxc@30330000 {
251			compatible = "nxp,imx-iomuxc";
252			reg = <0x30330000 DT_SIZE_K(64)>;
253			status = "okay";
254			pinctrl: pinctrl {
255				status = "okay";
256				compatible = "nxp,imx7d-pinctrl";
257			};
258		};
259
260		i2c1: i2c@30a20000 {
261			compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
262			clock-frequency = <I2C_BITRATE_STANDARD>;
263			#address-cells = <1>;
264			#size-cells = <0>;
265			reg = <0x30a20000 0x10000>;
266			interrupts = <35 0>;
267			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
268					       RDC_DOMAIN_PERM_RW)|\
269			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
270					       RDC_DOMAIN_PERM_RW))>;
271			status = "disabled";
272		};
273
274		i2c2: i2c@30a30000 {
275			compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
276			clock-frequency = <I2C_BITRATE_STANDARD>;
277			#address-cells = <1>;
278			#size-cells = <0>;
279			reg = <0x30a30000 0x10000>;
280			interrupts = <36 0>;
281			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
282					       RDC_DOMAIN_PERM_RW)|\
283			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
284					       RDC_DOMAIN_PERM_RW))>;
285			status = "disabled";
286		};
287
288		i2c3: i2c@30a40000 {
289			compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
290			clock-frequency = <I2C_BITRATE_STANDARD>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293			reg = <0x30a40000 0x10000>;
294			interrupts = <37 0>;
295			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
296					       RDC_DOMAIN_PERM_RW)|\
297			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
298					       RDC_DOMAIN_PERM_RW))>;
299			status = "disabled";
300		};
301
302		i2c4: i2c@30a50000 {
303			compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
304			clock-frequency = <I2C_BITRATE_STANDARD>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307			reg = <0x30a50000 0x10000>;
308			interrupts = <38 0>;
309			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
310					       RDC_DOMAIN_PERM_RW)|\
311			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
312					       RDC_DOMAIN_PERM_RW))>;
313			status = "disabled";
314		};
315
316		pwm1: pwm@30660000 {
317			compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
318			reg = <0x30660000 0x10000>;
319			interrupts = <81 0>;
320			prescaler = <0>;
321			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
322					       RDC_DOMAIN_PERM_RW)|\
323			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
324					       RDC_DOMAIN_PERM_RW))>;
325			status = "disabled";
326			#pwm-cells = <2>;
327		};
328
329		pwm2: pwm@30670000 {
330			compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
331			reg = <0x30670000 0x10000>;
332			interrupts = <82 0>;
333			prescaler = <0>;
334			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
335					       RDC_DOMAIN_PERM_RW)|\
336			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
337					       RDC_DOMAIN_PERM_RW))>;
338			status = "disabled";
339			#pwm-cells = <2>;
340		};
341
342		pwm3: pwm@30680000 {
343			compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
344			reg = <0x30680000 0x10000>;
345			interrupts = <83 0>;
346			prescaler = <0>;
347			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
348					       RDC_DOMAIN_PERM_RW)|\
349			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
350					       RDC_DOMAIN_PERM_RW))>;
351			status = "disabled";
352			#pwm-cells = <2>;
353		};
354
355		pwm4: pwm@30690000 {
356			compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
357			reg = <0x30690000 0x10000>;
358			interrupts = <84 0>;
359			prescaler = <0>;
360			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
361					       RDC_DOMAIN_PERM_RW)|\
362			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
363					       RDC_DOMAIN_PERM_RW))>;
364			status = "disabled";
365			#pwm-cells = <2>;
366		};
367	};
368};
369
370&nvic {
371	arm,num-irq-priority-bits = <4>;
372};
373
374
375/*
376 * GPIO pinmux options. These options define the pinmux settings
377 * for GPIO ports on the package, so that the GPIO driver can
378 * select GPIO mux options during GPIO configuration.
379 */
380
381&gpio1 {
382	pinmux = <&mx7d_pad_lpsr_gpio1_io00__gpio1_io0>,
383	<&mx7d_pad_lpsr_gpio1_io01__gpio1_io1>,
384	<&mx7d_pad_lpsr_gpio1_io02__gpio1_io2>,
385	<&mx7d_pad_lpsr_gpio1_io03__gpio1_io3>,
386	<&mx7d_pad_lpsr_gpio1_io04__gpio1_io4>,
387	<&mx7d_pad_lpsr_gpio1_io05__gpio1_io5>,
388	<&mx7d_pad_lpsr_gpio1_io06__gpio1_io6>,
389	<&mx7d_pad_lpsr_gpio1_io07__gpio1_io7>,
390	<&mx7d_pad_gpio1_io08__gpio1_io8>,
391	<&mx7d_pad_gpio1_io09__gpio1_io9>,
392	<&mx7d_pad_gpio1_io10__gpio1_io10>,
393	<&mx7d_pad_gpio1_io11__gpio1_io11>,
394	<&mx7d_pad_gpio1_io12__gpio1_io12>,
395	<&mx7d_pad_gpio1_io13__gpio1_io13>,
396	<&mx7d_pad_gpio1_io14__gpio1_io14>,
397	<&mx7d_pad_gpio1_io15__gpio1_io15>;
398};
399
400&gpio2 {
401	pinmux = <&mx7d_pad_epdc_data00__gpio2_io0>,
402	<&mx7d_pad_epdc_data01__gpio2_io1>,
403	<&mx7d_pad_epdc_data02__gpio2_io2>,
404	<&mx7d_pad_epdc_data03__gpio2_io3>,
405	<&mx7d_pad_epdc_data04__gpio2_io4>,
406	<&mx7d_pad_epdc_data05__gpio2_io5>,
407	<&mx7d_pad_epdc_data06__gpio2_io6>,
408	<&mx7d_pad_epdc_data07__gpio2_io7>,
409	<&mx7d_pad_epdc_data08__gpio2_io8>,
410	<&mx7d_pad_epdc_data09__gpio2_io9>,
411	<&mx7d_pad_epdc_data10__gpio2_io10>,
412	<&mx7d_pad_epdc_data11__gpio2_io11>,
413	<&mx7d_pad_epdc_data12__gpio2_io12>,
414	<&mx7d_pad_epdc_data13__gpio2_io13>,
415	<&mx7d_pad_epdc_data14__gpio2_io14>,
416	<&mx7d_pad_epdc_data15__gpio2_io15>,
417	<&mx7d_pad_epdc_sdclk__gpio2_io16>,
418	<&mx7d_pad_epdc_sdle__gpio2_io17>,
419	<&mx7d_pad_epdc_sdoe__gpio2_io18>,
420	<&mx7d_pad_epdc_sdshr__gpio2_io19>,
421	<&mx7d_pad_epdc_sdce0__gpio2_io20>,
422	<&mx7d_pad_epdc_sdce1__gpio2_io21>,
423	<&mx7d_pad_epdc_sdce2__gpio2_io22>,
424	<&mx7d_pad_epdc_sdce3__gpio2_io23>,
425	<&mx7d_pad_epdc_gdclk__gpio2_io24>,
426	<&mx7d_pad_epdc_gdoe__gpio2_io25>,
427	<&mx7d_pad_epdc_gdrl__gpio2_io26>,
428	<&mx7d_pad_epdc_gdsp__gpio2_io27>,
429	<&mx7d_pad_epdc_bdr0__gpio2_io28>,
430	<&mx7d_pad_epdc_bdr1__gpio2_io29>,
431	<&mx7d_pad_epdc_pwr_com__gpio2_io30>,
432	<&mx7d_pad_epdc_pwr_stat__gpio2_io31>;
433};
434
435&gpio3 {
436	pinmux = <&mx7d_pad_lcd_clk__gpio3_io0>,
437	<&mx7d_pad_lcd_enable__gpio3_io1>,
438	<&mx7d_pad_lcd_hsync__gpio3_io2>,
439	<&mx7d_pad_lcd_vsync__gpio3_io3>,
440	<&mx7d_pad_lcd_reset__gpio3_io4>,
441	<&mx7d_pad_lcd_data00__gpio3_io5>,
442	<&mx7d_pad_lcd_data01__gpio3_io6>,
443	<&mx7d_pad_lcd_data02__gpio3_io7>,
444	<&mx7d_pad_lcd_data03__gpio3_io8>,
445	<&mx7d_pad_lcd_data04__gpio3_io9>,
446	<&mx7d_pad_lcd_data05__gpio3_io10>,
447	<&mx7d_pad_lcd_data06__gpio3_io11>,
448	<&mx7d_pad_lcd_data07__gpio3_io12>,
449	<&mx7d_pad_lcd_data08__gpio3_io13>,
450	<&mx7d_pad_lcd_data09__gpio3_io14>,
451	<&mx7d_pad_lcd_data10__gpio3_io15>,
452	<&mx7d_pad_lcd_data11__gpio3_io16>,
453	<&mx7d_pad_lcd_data12__gpio3_io17>,
454	<&mx7d_pad_lcd_data13__gpio3_io18>,
455	<&mx7d_pad_lcd_data14__gpio3_io19>,
456	<&mx7d_pad_lcd_data15__gpio3_io20>,
457	<&mx7d_pad_lcd_data16__gpio3_io21>,
458	<&mx7d_pad_lcd_data17__gpio3_io22>,
459	<&mx7d_pad_lcd_data18__gpio3_io23>,
460	<&mx7d_pad_lcd_data19__gpio3_io24>,
461	<&mx7d_pad_lcd_data20__gpio3_io25>,
462	<&mx7d_pad_lcd_data21__gpio3_io26>,
463	<&mx7d_pad_lcd_data22__gpio3_io27>,
464	<&mx7d_pad_lcd_data23__gpio3_io28>;
465};
466
467&gpio4 {
468	pinmux = <&mx7d_pad_uart1_rx_data__gpio4_io0>,
469	<&mx7d_pad_uart1_tx_data__gpio4_io1>,
470	<&mx7d_pad_uart2_rx_data__gpio4_io2>,
471	<&mx7d_pad_uart2_tx_data__gpio4_io3>,
472	<&mx7d_pad_uart3_rx_data__gpio4_io4>,
473	<&mx7d_pad_uart3_tx_data__gpio4_io5>,
474	<&mx7d_pad_uart3_rts_b__gpio4_io6>,
475	<&mx7d_pad_uart3_cts_b__gpio4_io7>,
476	<&mx7d_pad_i2c1_scl__gpio4_io8>,
477	<&mx7d_pad_i2c1_sda__gpio4_io9>,
478	<&mx7d_pad_i2c2_scl__gpio4_io10>,
479	<&mx7d_pad_i2c2_sda__gpio4_io11>,
480	<&mx7d_pad_i2c3_scl__gpio4_io12>,
481	<&mx7d_pad_i2c3_sda__gpio4_io13>,
482	<&mx7d_pad_i2c4_scl__gpio4_io14>,
483	<&mx7d_pad_i2c4_sda__gpio4_io15>,
484	<&mx7d_pad_ecspi1_sclk__gpio4_io16>,
485	<&mx7d_pad_ecspi1_mosi__gpio4_io17>,
486	<&mx7d_pad_ecspi1_miso__gpio4_io18>,
487	<&mx7d_pad_ecspi1_ss0__gpio4_io19>,
488	<&mx7d_pad_ecspi2_sclk__gpio4_io20>,
489	<&mx7d_pad_ecspi2_mosi__gpio4_io21>,
490	<&mx7d_pad_ecspi2_miso__gpio4_io22>,
491	<&mx7d_pad_ecspi2_ss0__gpio4_io23>;
492};
493
494&gpio5 {
495	pinmux = <&mx7d_pad_sd1_cd_b__gpio5_io0>,
496	<&mx7d_pad_sd1_wp__gpio5_io1>,
497	<&mx7d_pad_sd1_reset_b__gpio5_io2>,
498	<&mx7d_pad_sd1_clk__gpio5_io3>,
499	<&mx7d_pad_sd1_cmd__gpio5_io4>,
500	<&mx7d_pad_sd1_data0__gpio5_io5>,
501	<&mx7d_pad_sd1_data1__gpio5_io6>,
502	<&mx7d_pad_sd1_data2__gpio5_io7>,
503	<&mx7d_pad_sd1_data3__gpio5_io8>,
504	<&mx7d_pad_sd2_cd_b__gpio5_io9>,
505	<&mx7d_pad_sd2_wp__gpio5_io10>,
506	<&mx7d_pad_sd2_reset_b__gpio5_io11>,
507	<&mx7d_pad_sd2_clk__gpio5_io12>,
508	<&mx7d_pad_sd2_cmd__gpio5_io13>,
509	<&mx7d_pad_sd2_data0__gpio5_io14>,
510	<&mx7d_pad_sd2_data1__gpio5_io15>,
511	<&mx7d_pad_sd2_data2__gpio5_io16>,
512	<&mx7d_pad_sd2_data3__gpio5_io17>;
513};
514
515&gpio6 {
516	pinmux = <&mx7d_pad_sd3_clk__gpio6_io0>,
517	<&mx7d_pad_sd3_cmd__gpio6_io1>,
518	<&mx7d_pad_sd3_data0__gpio6_io2>,
519	<&mx7d_pad_sd3_data1__gpio6_io3>,
520	<&mx7d_pad_sd3_data2__gpio6_io4>,
521	<&mx7d_pad_sd3_data3__gpio6_io5>,
522	<&mx7d_pad_sd3_data4__gpio6_io6>,
523	<&mx7d_pad_sd3_data5__gpio6_io7>,
524	<&mx7d_pad_sd3_data6__gpio6_io8>,
525	<&mx7d_pad_sd3_data7__gpio6_io9>,
526	<&mx7d_pad_sd3_strobe__gpio6_io10>,
527	<&mx7d_pad_sd3_reset_b__gpio6_io11>,
528	<&mx7d_pad_sai1_rx_data__gpio6_io12>,
529	<&mx7d_pad_sai1_tx_bclk__gpio6_io13>,
530	<&mx7d_pad_sai1_tx_sync__gpio6_io14>,
531	<&mx7d_pad_sai1_tx_data__gpio6_io15>,
532	<&mx7d_pad_sai1_rx_sync__gpio6_io16>,
533	<&mx7d_pad_sai1_rx_bclk__gpio6_io17>,
534	<&mx7d_pad_sai1_mclk__gpio6_io18>,
535	<&mx7d_pad_sai2_tx_sync__gpio6_io19>,
536	<&mx7d_pad_sai2_tx_bclk__gpio6_io20>,
537	<&mx7d_pad_sai2_rx_data__gpio6_io21>,
538	<&mx7d_pad_sai2_tx_data__gpio6_io22>;
539};
540
541&gpio7 {
542	pinmux = <&mx7d_pad_enet1_rgmii_rd0__gpio7_io0>,
543	<&mx7d_pad_enet1_rgmii_rd1__gpio7_io1>,
544	<&mx7d_pad_enet1_rgmii_rd2__gpio7_io2>,
545	<&mx7d_pad_enet1_rgmii_rd3__gpio7_io3>,
546	<&mx7d_pad_enet1_rgmii_rx_ctl__gpio7_io4>,
547	<&mx7d_pad_enet1_rgmii_rxc__gpio7_io5>,
548	<&mx7d_pad_enet1_rgmii_td0__gpio7_io6>,
549	<&mx7d_pad_enet1_rgmii_td1__gpio7_io7>,
550	<&mx7d_pad_enet1_rgmii_td2__gpio7_io8>,
551	<&mx7d_pad_enet1_rgmii_td3__gpio7_io9>,
552	<&mx7d_pad_enet1_rgmii_tx_ctl__gpio7_io10>,
553	<&mx7d_pad_enet1_rgmii_txc__gpio7_io11>,
554	<&mx7d_pad_enet1_tx_clk__gpio7_io12>,
555	<&mx7d_pad_enet1_rx_clk__gpio7_io13>,
556	<&mx7d_pad_enet1_crs__gpio7_io14>,
557	<&mx7d_pad_enet1_col__gpio7_io15>;
558};
559