1/* 2 * Copyright (c) 2018, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-m.dtsi> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/rdc/imx_rdc.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-a9"; 21 reg = <0>; 22 status = "disabled"; 23 }; 24 25 cpu@1 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <1>; 29 }; 30 }; 31 32 tcml:memory@1fff8000 { 33 compatible = "nxp,imx-itcm"; 34 reg = <0x1fff8000 DT_SIZE_K(32)>; 35 }; 36 37 tcmu:memory@20000000 { 38 compatible = "nxp,imx-dtcm"; 39 reg = <0x20000000 DT_SIZE_K(32)>; 40 }; 41 42 ocram_s:memory@208f8000 { 43 device_type = "memory"; 44 compatible = "nxp,imx-sys-bus"; 45 reg = <0x208f8000 DT_SIZE_K(16)>; 46 }; 47 48 ocram:memory@20900000 { 49 device_type = "memory"; 50 compatible = "nxp,imx-sys-bus"; 51 reg = <0x20900000 DT_SIZE_K(128)>; 52 }; 53 54 ddr:memory@80000000 { 55 device_type = "memory"; 56 compatible = "nxp,imx-sys-bus"; 57 reg = <0x80000000 0x60000000>; 58 }; 59 60 flash:memory@DT_FLASH_ADDR { 61 compatible = "soc-nv-flash"; 62 reg = <DT_ADDR(DT_FLASH_ADDR) DT_FLASH_SIZE>; 63 }; 64 65 sram:memory@DT_SRAM_ADDR { 66 reg = <DT_ADDR(DT_SRAM_ADDR) DT_SRAM_SIZE>; 67 }; 68 69 soc { 70 uart1:uart@42020000 { 71 compatible = "nxp,imx-uart"; 72 reg = <0x42020000 0x00004000>; 73 interrupts = <26 0>; 74 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 75 RDC_DOMAIN_PERM_RW)|\ 76 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 77 RDC_DOMAIN_PERM_RW))>; 78 status = "disabled"; 79 }; 80 81 uart2:uart@421e8000 { 82 compatible = "nxp,imx-uart"; 83 reg = <0x421e8000 0x00004000>; 84 interrupts = <27 0>; 85 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 86 RDC_DOMAIN_PERM_RW)|\ 87 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 88 RDC_DOMAIN_PERM_RW))>; 89 status = "disabled"; 90 }; 91 92 uart3:uart@421ec000 { 93 compatible = "nxp,imx-uart"; 94 reg = <0x421ec000 0x00004000>; 95 interrupts = <28 0>; 96 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 97 RDC_DOMAIN_PERM_RW)|\ 98 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 99 RDC_DOMAIN_PERM_RW))>; 100 status = "disabled"; 101 }; 102 103 uart4:uart@421f0000 { 104 compatible = "nxp,imx-uart"; 105 reg = <0x421f0000 0x00004000>; 106 interrupts = <29 0>; 107 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 108 RDC_DOMAIN_PERM_RW)|\ 109 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 110 RDC_DOMAIN_PERM_RW))>; 111 status = "disabled"; 112 }; 113 114 uart5:uart@421f4000 { 115 compatible = "nxp,imx-uart"; 116 reg = <0x421f4000 0x00004000>; 117 interrupts = <30 0>; 118 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 119 RDC_DOMAIN_PERM_RW)|\ 120 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 121 RDC_DOMAIN_PERM_RW))>; 122 status = "disabled"; 123 }; 124 125 uart6:uart@422a0000 { 126 compatible = "nxp,imx-uart"; 127 reg = <0x422a0000 0x00004000>; 128 interrupts = <17 0>; 129 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 130 RDC_DOMAIN_PERM_RW)|\ 131 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 132 RDC_DOMAIN_PERM_RW))>; 133 status = "disabled"; 134 }; 135 136 gpio1:gpio@4209c000 { 137 compatible = "nxp,imx-gpio"; 138 reg = <0x4209c000 0x4000>; 139 interrupts = <66 0>, <67 0>; 140 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 141 RDC_DOMAIN_PERM_RW)|\ 142 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 143 RDC_DOMAIN_PERM_RW))>; 144 gpio-controller; 145 #gpio-cells = <2>; 146 status = "disabled"; 147 }; 148 149 gpio2:gpio@420a0000 { 150 compatible = "nxp,imx-gpio"; 151 reg = <0x420a0000 0x4000>; 152 interrupts = <68 0>, <69 0>; 153 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 154 RDC_DOMAIN_PERM_RW)|\ 155 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 156 RDC_DOMAIN_PERM_RW))>; 157 gpio-controller; 158 #gpio-cells = <2>; 159 status = "disabled"; 160 }; 161 162 gpio3:gpio@420a4000 { 163 compatible = "nxp,imx-gpio"; 164 reg = <0x420a4000 0x4000>; 165 interrupts = <70 0>, <71 0>; 166 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 167 RDC_DOMAIN_PERM_RW)|\ 168 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 169 RDC_DOMAIN_PERM_RW))>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 status = "disabled"; 173 }; 174 175 gpio4:gpio@420a8000 { 176 compatible = "nxp,imx-gpio"; 177 reg = <0x420a8000 0x4000>; 178 interrupts = <72 0>, <73 0>; 179 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 180 RDC_DOMAIN_PERM_RW)|\ 181 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 182 RDC_DOMAIN_PERM_RW))>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 status = "disabled"; 186 }; 187 188 gpio5:gpio@420ac000 { 189 compatible = "nxp,imx-gpio"; 190 reg = <0x420ac000 0x4000>; 191 interrupts = <74 0>, <75 0>; 192 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 193 RDC_DOMAIN_PERM_RW)|\ 194 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 195 RDC_DOMAIN_PERM_RW))>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 status = "disabled"; 199 }; 200 201 gpio6:gpio@420b0000 { 202 compatible = "nxp,imx-gpio"; 203 reg = <0x420b0000 0x4000>; 204 interrupts = <76 0>, <77 0>; 205 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 206 RDC_DOMAIN_PERM_RW)|\ 207 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 208 RDC_DOMAIN_PERM_RW))>; 209 gpio-controller; 210 #gpio-cells = <2>; 211 status = "disabled"; 212 }; 213 214 gpio7:gpio@420b4000 { 215 compatible = "nxp,imx-gpio"; 216 reg = <0x420b4000 0x4000>; 217 interrupts = <78 0>, <79 0>; 218 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 219 RDC_DOMAIN_PERM_RW)|\ 220 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 221 RDC_DOMAIN_PERM_RW))>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 status = "disabled"; 225 }; 226 227 mub:mu@4229c000 { 228 compatible = "nxp,imx-mu"; 229 reg = <0x4229c000 0x4000>; 230 interrupts = <99 0>; 231 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 232 RDC_DOMAIN_PERM_RW)|\ 233 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 234 RDC_DOMAIN_PERM_RW))>; 235 status = "disabled"; 236 }; 237 238 epit1:epit@420d0000 { 239 compatible = "nxp,imx-epit"; 240 reg = <0x420d0000 0x4000>; 241 interrupts = <56 0>; 242 prescaler = <0>; 243 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 244 RDC_DOMAIN_PERM_RW)|\ 245 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 246 RDC_DOMAIN_PERM_RW))>; 247 status = "disabled"; 248 }; 249 250 iomuxc: iomuxc@420e0000 { 251 compatible = "nxp,imx-iomuxc"; 252 reg = <0x420e0000 0x4000>; 253 status = "okay"; 254 pinctrl: pinctrl { 255 status = "okay"; 256 /* iMX6 has same IOMUXC IP block as RT10xx series */ 257 compatible = "nxp,mcux-rt-pinctrl"; 258 }; 259 }; 260 261 epit2:epit@420d4000 { 262 compatible = "nxp,imx-epit"; 263 reg = <0x420d4000 0x4000>; 264 interrupts = <57 0>; 265 prescaler = <0>; 266 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 267 RDC_DOMAIN_PERM_RW)|\ 268 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 269 RDC_DOMAIN_PERM_RW))>; 270 status = "disabled"; 271 }; 272 273 i2c1: i2c@421a0000 { 274 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 275 clock-frequency = <I2C_BITRATE_STANDARD>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0x421a0000 0x4000>; 279 interrupts = <36 0>; 280 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 281 RDC_DOMAIN_PERM_RW)|\ 282 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 283 RDC_DOMAIN_PERM_RW))>; 284 status = "disabled"; 285 }; 286 287 i2c2: i2c@421a4000 { 288 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 289 clock-frequency = <I2C_BITRATE_STANDARD>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x421a4000 0x4000>; 293 interrupts = <37 0>; 294 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 295 RDC_DOMAIN_PERM_RW)|\ 296 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 297 RDC_DOMAIN_PERM_RW))>; 298 status = "disabled"; 299 }; 300 301 i2c3: i2c@421a8000 { 302 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 303 clock-frequency = <I2C_BITRATE_STANDARD>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 reg = <0x421a8000 0x4000>; 307 interrupts = <38 0>; 308 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 309 RDC_DOMAIN_PERM_RW)|\ 310 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 311 RDC_DOMAIN_PERM_RW))>; 312 status = "disabled"; 313 }; 314 315 i2c4: i2c@421f8000 { 316 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 317 clock-frequency = <I2C_BITRATE_STANDARD>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x421f8000 0x4000>; 321 interrupts = <35 0>; 322 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 323 RDC_DOMAIN_PERM_RW)|\ 324 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 325 RDC_DOMAIN_PERM_RW))>; 326 status = "disabled"; 327 }; 328 329 pwm1: pwm@42080000 { 330 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 331 reg = <0x42080000 0x4000>; 332 interrupts = <83 0>; 333 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 334 RDC_DOMAIN_PERM_RW)|\ 335 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 336 RDC_DOMAIN_PERM_RW))>; 337 prescaler = <0>; 338 #pwm-cells = <2>; 339 status = "disabled"; 340 }; 341 342 pwm2: pwm@42084000 { 343 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 344 reg = <0x42084000 0x4000>; 345 interrupts = <84 0>; 346 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 347 RDC_DOMAIN_PERM_RW)|\ 348 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 349 RDC_DOMAIN_PERM_RW))>; 350 prescaler = <0>; 351 #pwm-cells = <2>; 352 status = "disabled"; 353 }; 354 355 pwm3: pwm@42088000 { 356 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 357 reg = <0x42088000 0x4000>; 358 interrupts = <85 0>; 359 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 360 RDC_DOMAIN_PERM_RW)|\ 361 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 362 RDC_DOMAIN_PERM_RW))>; 363 prescaler = <0>; 364 #pwm-cells = <2>; 365 status = "disabled"; 366 }; 367 368 pwm4: pwm@4208c000 { 369 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 370 reg = <0x4208c000 0x4000>; 371 interrupts = <86 0>; 372 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 373 RDC_DOMAIN_PERM_RW)|\ 374 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 375 RDC_DOMAIN_PERM_RW))>; 376 prescaler = <0>; 377 #pwm-cells = <2>; 378 status = "disabled"; 379 }; 380 381 382 pwm5: pwm@422a4000 { 383 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 384 reg = <0x422a4000 0x4000>; 385 interrupts = <83 0>; 386 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 387 RDC_DOMAIN_PERM_RW)|\ 388 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 389 RDC_DOMAIN_PERM_RW))>; 390 prescaler = <0>; 391 #pwm-cells = <2>; 392 status = "disabled"; 393 }; 394 395 pwm6: pwm@422a8000 { 396 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 397 reg = <0x422a8000 0x4000>; 398 interrupts = <84 0>; 399 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 400 RDC_DOMAIN_PERM_RW)|\ 401 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 402 RDC_DOMAIN_PERM_RW))>; 403 prescaler = <0>; 404 #pwm-cells = <2>; 405 status = "disabled"; 406 }; 407 408 pwm7: pwm@422ac000 { 409 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 410 reg = <0x422ac000 0x4000>; 411 interrupts = <85 0>; 412 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 413 RDC_DOMAIN_PERM_RW)|\ 414 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 415 RDC_DOMAIN_PERM_RW))>; 416 prescaler = <0>; 417 #pwm-cells = <2>; 418 status = "disabled"; 419 }; 420 421 pwm8: pwm@422ab000 { 422 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 423 reg = <0x422ab000 0x4000>; 424 interrupts = <86 0>; 425 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 426 RDC_DOMAIN_PERM_RW)|\ 427 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 428 RDC_DOMAIN_PERM_RW))>; 429 prescaler = <0>; 430 #pwm-cells = <2>; 431 status = "disabled"; 432 }; 433 434 adc1: adc@42280000 { 435 compatible = "nxp,vf610-adc"; 436 reg = <0x42280000 0x4000>; 437 clk-source = <1>; 438 clk-divider = <2>; 439 interrupts = <100 0>; 440 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 441 RDC_DOMAIN_PERM_RW)|\ 442 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 443 RDC_DOMAIN_PERM_RW))>; 444 status = "disabled"; 445 #io-channel-cells = <1>; 446 }; 447 448 adc2: adc@42284000 { 449 compatible = "nxp,vf610-adc"; 450 reg = <0x42284000 0x4000>; 451 clk-source = <1>; 452 clk-divider = <2>; 453 interrupts = <101 0>; 454 rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ 455 RDC_DOMAIN_PERM_RW)|\ 456 RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ 457 RDC_DOMAIN_PERM_RW))>; 458 status = "disabled"; 459 #io-channel-cells = <1>; 460 }; 461 }; 462}; 463 464&nvic { 465 arm,num-irq-priority-bits = <4>; 466}; 467 468/* 469 * GPIO pinmux options. These options define the pinmux settings 470 * for GPIO ports on the package, so that the GPIO driver can 471 * select GPIO mux options during GPIO configuration. 472 */ 473 474&gpio1 { 475 pinmux = <&mx6sx_pad_gpio1_io00__gpio1_io_0>, 476 <&mx6sx_pad_gpio1_io01__gpio1_io_1>, 477 <&mx6sx_pad_gpio1_io02__gpio1_io_2>, 478 <&mx6sx_pad_gpio1_io03__gpio1_io_3>, 479 <&mx6sx_pad_gpio1_io04__gpio1_io_4>, 480 <&mx6sx_pad_gpio1_io05__gpio1_io_5>, 481 <&mx6sx_pad_gpio1_io06__gpio1_io_6>, 482 <&mx6sx_pad_gpio1_io07__gpio1_io_7>, 483 <&mx6sx_pad_gpio1_io08__gpio1_io_8>, 484 <&mx6sx_pad_gpio1_io09__gpio1_io_9>, 485 <&mx6sx_pad_gpio1_io10__gpio1_io_10>, 486 <&mx6sx_pad_gpio1_io11__gpio1_io_11>, 487 <&mx6sx_pad_gpio1_io12__gpio1_io_12>, 488 <&mx6sx_pad_gpio1_io13__gpio1_io_13>, 489 <&mx6sx_pad_csi_data00__gpio1_io_14>, 490 <&mx6sx_pad_csi_data01__gpio1_io_15>, 491 <&mx6sx_pad_csi_data02__gpio1_io_16>, 492 <&mx6sx_pad_csi_data03__gpio1_io_17>, 493 <&mx6sx_pad_csi_data04__gpio1_io_18>, 494 <&mx6sx_pad_csi_data05__gpio1_io_19>, 495 <&mx6sx_pad_csi_data06__gpio1_io_20>, 496 <&mx6sx_pad_csi_data07__gpio1_io_21>, 497 <&mx6sx_pad_csi_hsync__gpio1_io_22>, 498 <&mx6sx_pad_csi_mclk__gpio1_io_23>, 499 <&mx6sx_pad_csi_pixclk__gpio1_io_24>, 500 <&mx6sx_pad_csi_vsync__gpio1_io_25>; 501}; 502 503&gpio2 { 504 pinmux = <&mx6sx_pad_enet1_col__gpio2_io_0>, 505 <&mx6sx_pad_enet1_crs__gpio2_io_1>, 506 <&mx6sx_pad_enet1_mdc__gpio2_io_2>, 507 <&mx6sx_pad_enet1_mdio__gpio2_io_3>, 508 <&mx6sx_pad_enet1_rx_clk__gpio2_io_4>, 509 <&mx6sx_pad_enet1_tx_clk__gpio2_io_5>, 510 <&mx6sx_pad_enet2_col__gpio2_io_6>, 511 <&mx6sx_pad_enet2_crs__gpio2_io_7>, 512 <&mx6sx_pad_enet2_rx_clk__gpio2_io_8>, 513 <&mx6sx_pad_enet2_tx_clk__gpio2_io_9>, 514 <&mx6sx_pad_key_col0__gpio2_io_10>, 515 <&mx6sx_pad_key_col1__gpio2_io_11>, 516 <&mx6sx_pad_key_col2__gpio2_io_12>, 517 <&mx6sx_pad_key_col3__gpio2_io_13>, 518 <&mx6sx_pad_key_col4__gpio2_io_14>, 519 <&mx6sx_pad_key_row0__gpio2_io_15>, 520 <&mx6sx_pad_key_row1__gpio2_io_16>, 521 <&mx6sx_pad_key_row2__gpio2_io_17>, 522 <&mx6sx_pad_key_row3__gpio2_io_18>, 523 <&mx6sx_pad_key_row4__gpio2_io_19>; 524}; 525 526&gpio3 { 527 pinmux = <&mx6sx_pad_lcd1_clk__gpio3_io_0>, 528 <&mx6sx_pad_lcd1_data00__gpio3_io_1>, 529 <&mx6sx_pad_lcd1_data01__gpio3_io_2>, 530 <&mx6sx_pad_lcd1_data02__gpio3_io_3>, 531 <&mx6sx_pad_lcd1_data03__gpio3_io_4>, 532 <&mx6sx_pad_lcd1_data04__gpio3_io_5>, 533 <&mx6sx_pad_lcd1_data05__gpio3_io_6>, 534 <&mx6sx_pad_lcd1_data06__gpio3_io_7>, 535 <&mx6sx_pad_lcd1_data07__gpio3_io_8>, 536 <&mx6sx_pad_lcd1_data08__gpio3_io_9>, 537 <&mx6sx_pad_lcd1_data09__gpio3_io_10>, 538 <&mx6sx_pad_lcd1_data10__gpio3_io_11>, 539 <&mx6sx_pad_lcd1_data11__gpio3_io_12>, 540 <&mx6sx_pad_lcd1_data12__gpio3_io_13>, 541 <&mx6sx_pad_lcd1_data13__gpio3_io_14>, 542 <&mx6sx_pad_lcd1_data14__gpio3_io_15>, 543 <&mx6sx_pad_lcd1_data15__gpio3_io_16>, 544 <&mx6sx_pad_lcd1_data16__gpio3_io_17>, 545 <&mx6sx_pad_lcd1_data17__gpio3_io_18>, 546 <&mx6sx_pad_lcd1_data18__gpio3_io_19>, 547 <&mx6sx_pad_lcd1_data19__gpio3_io_20>, 548 <&mx6sx_pad_lcd1_data20__gpio3_io_21>, 549 <&mx6sx_pad_lcd1_data21__gpio3_io_22>, 550 <&mx6sx_pad_lcd1_data22__gpio3_io_23>, 551 <&mx6sx_pad_lcd1_data23__gpio3_io_24>, 552 <&mx6sx_pad_lcd1_enable__gpio3_io_25>, 553 <&mx6sx_pad_lcd1_hsync__gpio3_io_26>, 554 <&mx6sx_pad_lcd1_reset__gpio3_io_27>, 555 <&mx6sx_pad_lcd1_vsync__gpio3_io_28>; 556}; 557 558&gpio4 { 559 pinmux = <&mx6sx_pad_nand_ale__gpio4_io_0>, 560 <&mx6sx_pad_nand_ce0_b__gpio4_io_1>, 561 <&mx6sx_pad_nand_ce1_b__gpio4_io_2>, 562 <&mx6sx_pad_nand_cle__gpio4_io_3>, 563 <&mx6sx_pad_nand_data00__gpio4_io_4>, 564 <&mx6sx_pad_nand_data01__gpio4_io_5>, 565 <&mx6sx_pad_nand_data02__gpio4_io_6>, 566 <&mx6sx_pad_nand_data03__gpio4_io_7>, 567 <&mx6sx_pad_nand_data04__gpio4_io_8>, 568 <&mx6sx_pad_nand_data05__gpio4_io_9>, 569 <&mx6sx_pad_nand_data06__gpio4_io_10>, 570 <&mx6sx_pad_nand_data07__gpio4_io_11>, 571 <&mx6sx_pad_nand_re_b__gpio4_io_12>, 572 <&mx6sx_pad_nand_ready_b__gpio4_io_13>, 573 <&mx6sx_pad_nand_we_b__gpio4_io_14>, 574 <&mx6sx_pad_nand_wp_b__gpio4_io_15>, 575 <&mx6sx_pad_qspi1a_data0__gpio4_io_16>, 576 <&mx6sx_pad_qspi1a_data1__gpio4_io_17>, 577 <&mx6sx_pad_qspi1a_data2__gpio4_io_18>, 578 <&mx6sx_pad_qspi1a_data3__gpio4_io_19>, 579 <&mx6sx_pad_qspi1a_dqs__gpio4_io_20>, 580 <&mx6sx_pad_qspi1a_sclk__gpio4_io_21>, 581 <&mx6sx_pad_qspi1a_ss0_b__gpio4_io_22>, 582 <&mx6sx_pad_qspi1a_ss1_b__gpio4_io_23>, 583 <&mx6sx_pad_qspi1b_data0__gpio4_io_24>, 584 <&mx6sx_pad_qspi1b_data1__gpio4_io_25>, 585 <&mx6sx_pad_qspi1b_data2__gpio4_io_26>, 586 <&mx6sx_pad_qspi1b_data3__gpio4_io_27>, 587 <&mx6sx_pad_qspi1b_dqs__gpio4_io_28>, 588 <&mx6sx_pad_qspi1b_sclk__gpio4_io_29>, 589 <&mx6sx_pad_qspi1b_ss0_b__gpio4_io_30>, 590 <&mx6sx_pad_qspi1b_ss1_b__gpio4_io_31>; 591}; 592 593&gpio5 { 594 pinmux = <&mx6sx_pad_rgmii1_rd0__gpio5_io_0>, 595 <&mx6sx_pad_rgmii1_rd1__gpio5_io_1>, 596 <&mx6sx_pad_rgmii1_rd2__gpio5_io_2>, 597 <&mx6sx_pad_rgmii1_rd3__gpio5_io_3>, 598 <&mx6sx_pad_rgmii1_rx_ctl__gpio5_io_4>, 599 <&mx6sx_pad_rgmii1_rxc__gpio5_io_5>, 600 <&mx6sx_pad_rgmii1_td0__gpio5_io_6>, 601 <&mx6sx_pad_rgmii1_td1__gpio5_io_7>, 602 <&mx6sx_pad_rgmii1_td2__gpio5_io_8>, 603 <&mx6sx_pad_rgmii1_td3__gpio5_io_9>, 604 <&mx6sx_pad_rgmii1_tx_ctl__gpio5_io_10>, 605 <&mx6sx_pad_rgmii1_txc__gpio5_io_11>, 606 <&mx6sx_pad_rgmii2_rd0__gpio5_io_12>, 607 <&mx6sx_pad_rgmii2_rd1__gpio5_io_13>, 608 <&mx6sx_pad_rgmii2_rd2__gpio5_io_14>, 609 <&mx6sx_pad_rgmii2_rd3__gpio5_io_15>, 610 <&mx6sx_pad_rgmii2_rx_ctl__gpio5_io_16>, 611 <&mx6sx_pad_rgmii2_rxc__gpio5_io_17>, 612 <&mx6sx_pad_rgmii2_td0__gpio5_io_18>, 613 <&mx6sx_pad_rgmii2_td1__gpio5_io_19>, 614 <&mx6sx_pad_rgmii2_td2__gpio5_io_20>, 615 <&mx6sx_pad_rgmii2_td3__gpio5_io_21>, 616 <&mx6sx_pad_rgmii2_tx_ctl__gpio5_io_22>, 617 <&mx6sx_pad_rgmii2_txc__gpio5_io_23>; 618}; 619 620&gpio6 { 621 pinmux = <&mx6sx_pad_sd1_clk__gpio6_io_0>, 622 <&mx6sx_pad_sd1_cmd__gpio6_io_1>, 623 <&mx6sx_pad_sd1_data0__gpio6_io_2>, 624 <&mx6sx_pad_sd1_data1__gpio6_io_3>, 625 <&mx6sx_pad_sd1_data2__gpio6_io_4>, 626 <&mx6sx_pad_sd1_data3__gpio6_io_5>, 627 <&mx6sx_pad_sd2_clk__gpio6_io_6>, 628 <&mx6sx_pad_sd2_cmd__gpio6_io_7>, 629 <&mx6sx_pad_sd2_data0__gpio6_io_8>, 630 <&mx6sx_pad_sd2_data1__gpio6_io_9>, 631 <&mx6sx_pad_sd2_data2__gpio6_io_10>, 632 <&mx6sx_pad_sd2_data3__gpio6_io_11>, 633 <&mx6sx_pad_sd4_clk__gpio6_io_12>, 634 <&mx6sx_pad_sd4_cmd__gpio6_io_13>, 635 <&mx6sx_pad_sd4_data0__gpio6_io_14>, 636 <&mx6sx_pad_sd4_data1__gpio6_io_15>, 637 <&mx6sx_pad_sd4_data2__gpio6_io_16>, 638 <&mx6sx_pad_sd4_data3__gpio6_io_17>, 639 <&mx6sx_pad_sd4_data4__gpio6_io_18>, 640 <&mx6sx_pad_sd4_data5__gpio6_io_19>, 641 <&mx6sx_pad_sd4_data6__gpio6_io_20>, 642 <&mx6sx_pad_sd4_data7__gpio6_io_21>, 643 <&mx6sx_pad_sd4_reset_b__gpio6_io_22>; 644}; 645 646&gpio7 { 647 pinmux = <&mx6sx_pad_sd3_clk__gpio7_io_0>, 648 <&mx6sx_pad_sd3_cmd__gpio7_io_1>, 649 <&mx6sx_pad_sd3_data0__gpio7_io_2>, 650 <&mx6sx_pad_sd3_data1__gpio7_io_3>, 651 <&mx6sx_pad_sd3_data2__gpio7_io_4>, 652 <&mx6sx_pad_sd3_data3__gpio7_io_5>, 653 <&mx6sx_pad_sd3_data4__gpio7_io_6>, 654 <&mx6sx_pad_sd3_data5__gpio7_io_7>, 655 <&mx6sx_pad_sd3_data6__gpio7_io_8>, 656 <&mx6sx_pad_sd3_data7__gpio7_io_9>, 657 <&mx6sx_pad_usb_h_data__gpio7_io_10>, 658 <&mx6sx_pad_usb_h_strobe__gpio7_io_11>; 659}; 660
