1/*
2 * Copyright (c) 2021 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* NPCX9 series pinmux mapping table */
8#include "npcx9/npcx9-alts-map.dtsi"
9/* NPCX9 series mapping table between MIWU wui bits and source device */
10#include "npcx9/npcx9-miwus-wui-map.dtsi"
11/* NPCX9 series mapping table between MIWU groups and interrupts */
12#include "npcx9/npcx9-miwus-int-map.dtsi"
13/* NPCX9 series eSPI VW mapping table */
14#include "npcx9/npcx9-espi-vws-map.dtsi"
15/* NPCX9 series low-voltage io controls mapping table */
16#include "npcx9/npcx9-lvol-ctrl-map.dtsi"
17
18/* Device tree declarations of npcx soc family */
19#include "npcx.dtsi"
20
21/ {
22	def-io-conf-list {
23		pinmux = <&alt0_gpio_no_spip
24			   &alt0_gpio_no_fpip
25			   &alt1_no_pwrgd
26			   &alta_no_peci_en
27			   &altd_npsl_in1_sl
28			   &altd_npsl_in2_sl
29			   &altd_psl_in3_sl
30			   &altd_psl_in4_sl
31			   &alt7_no_ksi0_sl
32			   &alt7_no_ksi1_sl
33			   &alt7_no_ksi2_sl
34			   &alt7_no_ksi3_sl
35			   &alt7_no_ksi4_sl
36			   &alt7_no_ksi5_sl
37			   &alt7_no_ksi6_sl
38			   &alt7_no_ksi7_sl
39			   &alt8_no_kso00_sl
40			   &alt8_no_kso01_sl
41			   &alt8_no_kso02_sl
42			   &alt8_no_kso03_sl
43			   &alt8_no_kso04_sl
44			   &alt8_no_kso05_sl
45			   &alt8_no_kso06_sl
46			   &alt8_no_kso07_sl
47			   &alt9_no_kso08_sl
48			   &alt9_no_kso09_sl
49			   &alt9_no_kso10_sl
50			   &alt9_no_kso11_sl
51			   &alt9_no_kso12_sl
52			   &alt9_no_kso13_sl
53			   &alt9_no_kso14_sl
54			   &alt9_no_kso15_sl
55			   &alta_no_kso16_sl
56			   &alta_no_kso17_sl
57			   &altg_psl_gpo_sl>;
58	};
59
60	soc {
61		compatible = "nuvoton,npcx9", "nuvoton,npcx", "simple-bus";
62
63		/* Specific soc devices in npcx9 series */
64		itims: timer@400b0000 {
65			compatible = "nuvoton,npcx-itim-timer";
66			reg = <0x400b0000 0x2000
67			       0x400be000 0x2000>;
68			reg-names = "evt_itim", "sys_itim";
69			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
70				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
71			interrupts = <28 1>; /* Event timer interrupt */
72		};
73
74		uart1: serial@400e0000 {
75			compatible = "nuvoton,npcx-uart";
76			reg = <0x400E0000 0x2000>;
77			interrupts = <33 3>;
78			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
79			uart-rx = <&wui_cr_sin1>;
80			status = "disabled";
81		};
82
83		uart2: serial@400e2000 {
84			compatible = "nuvoton,npcx-uart";
85			reg = <0x400E2000 0x2000>;
86			interrupts = <32 3>;
87			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
88			uart-rx = <&wui_cr_sin2>;
89			status = "disabled";
90		};
91
92		uart3: serial@400e4000 {
93			compatible = "nuvoton,npcx-uart";
94			reg = <0x400E4000 0x2000>;
95			interrupts = <38 3>;
96			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
97			uart-rx = <&wui_cr_sin3>;
98			status = "disabled";
99		};
100
101		uart4: serial@400e6000 {
102			compatible = "nuvoton,npcx-uart";
103			reg = <0x400E6000 0x2000>;
104			interrupts = <39 3>;
105			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
106			uart-rx = <&wui_cr_sin4>;
107			status = "disabled";
108		};
109
110		/* Default clock and power settings in npcx9 series */
111		pcc: clock-controller@4000d000 {
112			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
113			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
114			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
115			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
116			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
117			apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
118			ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
119			pwdwn-ctl-val = <0xfb /* No FIU_PD */
120					 0xff
121					 0x1f /* No GDMA_PD */
122					 0xff
123					 0xfa
124					 0x7f /* No ESPI_PD */
125					 0xff
126					 0x31>;
127		};
128
129		/* Wake-up input source mapping for GPIOs in npcx9 series */
130		gpio0: gpio@40081000 {
131			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
132				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
133
134			lvol-maps = <&lvol_io00 &lvol_none &lvol_none &lvol_none
135				     &lvol_none &lvol_none &lvol_none &lvol_none>;
136		};
137
138		gpio1: gpio@40083000 {
139			wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
140				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
141
142			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
143				     &lvol_none &lvol_none &lvol_none &lvol_none>;
144		};
145
146		gpio2: gpio@40085000 {
147			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
148				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
149
150			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
151				     &lvol_none &lvol_none &lvol_none &lvol_none>;
152		};
153
154		gpio3: gpio@40087000 {
155			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
156				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
157
158			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
159				     &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>;
160		};
161
162		gpio4: gpio@40089000 {
163			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
164				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
165
166			lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none
167				     &lvol_none &lvol_none &lvol_none &lvol_none>;
168		};
169
170		gpio5: gpio@4008b000 {
171			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
172				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
173
174			lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
175				     &lvol_none &lvol_none &lvol_none &lvol_none>;
176		};
177
178		gpio6: gpio@4008d000 {
179			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
180				    &wui_io64 &wui_none &wui_io66 &wui_io67>;
181
182			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
183				     &lvol_io64 &lvol_none &lvol_io66 &lvol_none>;
184		};
185
186		gpio7: gpio@4008f000 {
187			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
188				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
189
190			lvol-maps = <&lvol_none &lvol_none &lvol_io72 &lvol_io73
191				     &lvol_io74 &lvol_io75 &lvol_none &lvol_none>;
192		};
193
194		gpio8: gpio@40091000 {
195			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
196				    &wui_none &wui_none &wui_none &wui_io87>;
197
198			lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_none
199				     &lvol_none &lvol_none &lvol_none &lvol_io87>;
200		};
201
202		gpio9: gpio@40093000 {
203			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
204				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
205
206			lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
207				     &lvol_none &lvol_none &lvol_none &lvol_none>;
208		};
209
210		gpioa: gpio@40095000 {
211			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
212				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
213
214			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
215				     &lvol_none &lvol_none &lvol_none &lvol_none>;
216		};
217
218		gpiob: gpio@40097000 {
219			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
220				    &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>;
221
222			lvol-maps = <&lvol_none &lvol_none &lvol_iob2 &lvol_iob3
223				     &lvol_iob4 &lvol_iob5 &lvol_none &lvol_none>;
224		};
225
226		gpioc: gpio@40099000 {
227			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
228				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
229
230			lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none
231				     &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>;
232		};
233
234		gpiod: gpio@4009b000 {
235			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
236				    &wui_iod4 &wui_iod5 &wui_none &wui_none>;
237
238			lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_none &lvol_none
239				     &lvol_none &lvol_none &lvol_none &lvol_none>;
240		};
241
242		gpioe: gpio@4009d000 {
243			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
244				    &wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
245
246			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_ioe3
247				     &lvol_ioe4 &lvol_none &lvol_none &lvol_none>;
248		};
249
250		gpiof: gpio@4009f000 {
251			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
252				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
253
254			lvol-maps = <&lvol_none &lvol_none &lvol_iof2 &lvol_iof3
255				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
256		};
257
258		/* ADC0 comparator configuration in npcx9 series */
259		adc0: adc@400d1000 {
260			channel-count = <12>;
261			threshold-count = <6>;
262		};
263
264		/* FIU0 configuration in npcx9 series */
265		qspi_fiu0: quadspi@40020000 {
266			clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
267		};
268
269		sha0: sha@13c {
270			compatible = "nuvoton,npcx-sha";
271			reg = <0x13c 0x3c>;
272			context-buffer-size = <212>;
273			status = "disabled";
274		};
275	};
276
277	soc-id {
278		chip-id = <0x09>;
279		revision-reg = <0x0000FFFC 4>;
280	};
281};
282