1/*
2 * Copyright (c) 2021 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* NPCX7 series pinmux mapping table */
8#include "npcx7/npcx7-alts-map.dtsi"
9/* NPCX7 series mapping table between MIWU wui bits and source device */
10#include "npcx7/npcx7-miwus-wui-map.dtsi"
11/* NPCX7 series mapping table between MIWU groups and interrupts */
12#include "npcx7/npcx7-miwus-int-map.dtsi"
13/* NPCX7 series eSPI VW mapping table */
14#include "npcx7/npcx7-espi-vws-map.dtsi"
15/* NPCX7 series low-voltage io controls mapping table */
16#include "npcx7/npcx7-lvol-ctrl-map.dtsi"
17
18/* Device tree declarations of npcx soc family */
19#include "npcx.dtsi"
20
21/ {
22	def-io-conf-list {
23		pinmux = <&alt0_gpio_no_spip
24			   &alt0_gpio_no_fpip
25			   &alt1_no_pwrgd
26			   &alta_no_peci_en
27			   &altd_npsl_in1_sl
28			   &altd_npsl_in2_sl
29			   &altd_psl_in3_sl
30			   &altd_psl_in4_sl
31			   &alt7_no_ksi0_sl
32			   &alt7_no_ksi1_sl
33			   &alt7_no_ksi2_sl
34			   &alt7_no_ksi3_sl
35			   &alt7_no_ksi4_sl
36			   &alt7_no_ksi5_sl
37			   &alt7_no_ksi6_sl
38			   &alt7_no_ksi7_sl
39			   &alt8_no_kso00_sl
40			   &alt8_no_kso01_sl
41			   &alt8_no_kso02_sl
42			   &alt8_no_kso03_sl
43			   &alt8_no_kso04_sl
44			   &alt8_no_kso05_sl
45			   &alt8_no_kso06_sl
46			   &alt8_no_kso07_sl
47			   &alt9_no_kso08_sl
48			   &alt9_no_kso09_sl
49			   &alt9_no_kso10_sl
50			   &alt9_no_kso11_sl
51			   &alt9_no_kso12_sl
52			   &alt9_no_kso13_sl
53			   &alt9_no_kso14_sl
54			   &alt9_no_kso15_sl
55			   &alta_no_kso16_sl
56			   &alta_no_kso17_sl>;
57	};
58
59	soc {
60		compatible = "nuvoton,npcx7", "nuvoton,npcx", "simple-bus";
61
62		/* Specific soc devices in npcx7 series */
63		itims: timer@400bc000 {
64			compatible = "nuvoton,npcx-itim-timer";
65			reg = <0x400bc000 0x2000
66			       0x400be000 0x2000>;
67			reg-names = "evt_itim", "sys_itim";
68			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3
69				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
70			interrupts = <46 1>; /* Event timer interrupt */
71		};
72
73		uart1: serial@400c4000 {
74			compatible = "nuvoton,npcx-uart";
75			reg = <0x400C4000 0x2000>;
76			interrupts = <33 3>;
77			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
78			uart-rx = <&wui_cr_sin1>;
79			status = "disabled";
80		};
81
82		uart2: serial@400c6000 {
83			compatible = "nuvoton,npcx-uart";
84			reg = <0x400C6000 0x2000>;
85			interrupts = <32 3>;
86			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>;
87			uart-rx = <&wui_cr_sin2>;
88			status = "disabled";
89		};
90
91		/* Default clock and power settings in npcx9 series */
92		pcc: clock-controller@4000d000 {
93			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
94			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
95			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
96			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
97			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
98			ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */
99			pwdwn-ctl-val = <0xfb /* No FIU_PD */
100					 0xff
101					 0x1f /* No GDMA_PD */
102					 0xff
103					 0xfa
104					 0x7f /* No ESPI_PD */
105					 0xe7>;
106		};
107
108		/* Wake-up input source mapping for GPIOs in npcx7 series */
109		gpio0: gpio@40081000 {
110			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
111				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
112
113			lvol-maps = <&lvol_io00 &lvol_none &lvol_none &lvol_none
114				     &lvol_none &lvol_none &lvol_none &lvol_none>;
115		};
116
117		gpio1: gpio@40083000 {
118			wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
119				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
120
121			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
122				     &lvol_none &lvol_none &lvol_none &lvol_none>;
123		};
124
125		gpio2: gpio@40085000 {
126			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
127				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
128
129			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
130				     &lvol_none &lvol_none &lvol_none &lvol_none>;
131		};
132
133		gpio3: gpio@40087000 {
134			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
135				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
136
137			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
138				     &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>;
139		};
140
141		gpio4: gpio@40089000 {
142			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
143				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
144
145			lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none
146				     &lvol_none &lvol_none &lvol_none &lvol_none>;
147		};
148
149		gpio5: gpio@4008b000 {
150			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
151				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
152
153			lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
154				     &lvol_none &lvol_none &lvol_none &lvol_none>;
155		};
156
157		gpio6: gpio@4008d000 {
158			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
159				    &wui_io64 &wui_none &wui_none &wui_io67>;
160
161			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
162				     &lvol_io64 &lvol_none &lvol_none &lvol_none>;
163		};
164
165		gpio7: gpio@4008f000 {
166			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
167				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
168
169			lvol-maps = <&lvol_none &lvol_none &lvol_io72 &lvol_io73
170				     &lvol_io74 &lvol_io75 &lvol_none &lvol_none>;
171		};
172
173		gpio8: gpio@40091000 {
174			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
175				    &wui_none &wui_none &wui_io86 &wui_io87>;
176
177			lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_none
178				     &lvol_none &lvol_none &lvol_io86 &lvol_io87>;
179		};
180
181		gpio9: gpio@40093000 {
182			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
183				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
184
185			lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
186				     &lvol_none &lvol_none &lvol_none &lvol_none>;
187		};
188
189		gpioa: gpio@40095000 {
190			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
191				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
192
193			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
194				     &lvol_none &lvol_none &lvol_none &lvol_none>;
195		};
196
197		gpiob: gpio@40097000 {
198			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
199				    &wui_iob4 &wui_iob5 &wui_none &wui_iob7>;
200
201			lvol-maps = <&lvol_none &lvol_none &lvol_iob2 &lvol_iob3
202				     &lvol_iob4 &lvol_iob5 &lvol_none &lvol_none>;
203		};
204
205		gpioc: gpio@40099000 {
206			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
207				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
208
209			lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none
210				     &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>;
211		};
212
213		gpiod: gpio@4009b000 {
214			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
215				    &wui_iod4 &wui_iod5 &wui_none &wui_iod7>;
216
217			lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_none &lvol_none
218				     &lvol_none &lvol_none &lvol_none &lvol_none>;
219		};
220
221		gpioe: gpio@4009d000 {
222			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
223				    &wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
224
225			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_ioe3
226				     &lvol_ioe4 &lvol_none &lvol_none &lvol_none>;
227		};
228
229		gpiof: gpio@4009f000 {
230			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
231				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
232
233			lvol-maps = <&lvol_none &lvol_none &lvol_iof2 &lvol_iof3
234				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
235		};
236
237		/* ADC0 comparator configuration in npcx7 series */
238		adc0: adc@400d1000 {
239			channel-count = <10>;
240			threshold-count = <3>;
241		};
242
243		/* FIU0 configuration in npcx7 series */
244		qspi_fiu0: quadspi@40020000 {
245			clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
246		};
247	};
248
249	soc-id {
250		chip-id = <0x07>;
251		revision-reg = <0x00007FFC 1>;
252	};
253
254	booter-variant {
255		hif-type-auto;
256	};
257};
258