1/*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* npcx4 series pinmux mapping table */
8#include "npcx4/npcx4-alts-map.dtsi"
9/* npcx4 series mapping table between MIWU wui bits and source device */
10#include "npcx4/npcx4-miwus-wui-map.dtsi"
11/* npcx4 series mapping table between MIWU groups and interrupts */
12#include "npcx4/npcx4-miwus-int-map.dtsi"
13/* npcx4 series eSPI VW mapping table */
14#include "npcx4/npcx4-espi-vws-map.dtsi"
15/* npcx4 series low-voltage io controls mapping table */
16#include "npcx4/npcx4-lvol-ctrl-map.dtsi"
17
18/* Device tree declarations of npcx soc family */
19#include "npcx.dtsi"
20
21/ {
22	def-io-conf-list {
23		pinmux = <&alt0_gpio_no_spip
24			  &alt0_gpio_no_fpip
25			  &alt1_no_pwrgd
26			  &alt7_no_ksi0_sl
27			  &alt7_no_ksi1_sl
28			  &alt7_no_ksi2_sl
29			  &alt7_no_ksi3_sl
30			  &alt7_no_ksi4_sl
31			  &alt7_no_ksi5_sl
32			  &alt7_no_ksi6_sl
33			  &alt7_no_ksi7_sl
34			  &alt8_no_kso00_sl
35			  &alt8_no_kso01_sl
36			  &alt8_no_kso02_sl
37			  &alt8_no_kso03_sl
38			  &alt8_no_kso04_sl
39			  &alt8_no_kso05_sl
40			  &alt8_no_kso06_sl
41			  &alt8_no_kso07_sl
42			  &alt9_no_kso08_sl
43			  &alt9_no_kso09_sl
44			  &alt9_no_kso10_sl
45			  &alt9_no_kso11_sl
46			  &alt9_no_kso12_sl
47			  &alt9_no_kso13_sl
48			  &alt9_no_kso14_sl
49			  &alt9_no_kso15_sl
50			  &alta_no_kso16_sl
51			  &alta_no_kso17_sl
52			  &alta_no_peci_en
53			  &altc_gpio97_sl_inv
54			  &altd_npsl_in1_sl
55			  &altd_npsl_in2_sl
56			  &altd_psl_in3_sl
57			  &altd_psl_in4_sl
58			  &altg_psl_gpo_sl>;
59	};
60
61	soc {
62		compatible = "nuvoton,npcx4", "nuvoton,npcx", "simple-bus";
63
64		/* Specific soc devices in npcx4 series */
65		itims: timer@400b0000 {
66			compatible = "nuvoton,npcx-itim-timer";
67			reg = <0x400b0000 0x2000
68			       0x400be000 0x2000>;
69			reg-names = "evt_itim", "sys_itim";
70			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
71				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
72			interrupts = <28 1>; /* Event timer interrupt */
73		};
74
75		uart1: serial@400e0000 {
76			compatible = "nuvoton,npcx-uart";
77			reg = <0x400E0000 0x2000>;
78			interrupts = <33 3>;
79			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
80			uart-rx = <&wui_cr_sin1>;
81			status = "disabled";
82		};
83
84		uart2: serial@400e2000 {
85			compatible = "nuvoton,npcx-uart";
86			reg = <0x400E2000 0x2000>;
87			interrupts = <32 3>;
88			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
89			uart-rx = <&wui_cr_sin2>;
90			status = "disabled";
91		};
92
93		uart3: serial@400e4000 {
94			compatible = "nuvoton,npcx-uart";
95			reg = <0x400E4000 0x2000>;
96			interrupts = <38 3>;
97			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
98			uart-rx = <&wui_cr_sin3>;
99			status = "disabled";
100		};
101
102		uart4: serial@400e6000 {
103			compatible = "nuvoton,npcx-uart";
104			reg = <0x400E6000 0x2000>;
105			interrupts = <39 3>;
106			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
107			uart-rx = <&wui_cr_sin4>;
108			status = "disabled";
109		};
110
111		/* Default clock and power settings in npcx4 series */
112		pcc: clock-controller@4000d000 {
113			clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */
114			core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
115			apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */
116			apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */
117			apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */
118			apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
119			ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */
120			pwdwn-ctl-val = <0xfb
121					 0xff
122					 0x1f /* No GDMA1_PD/GDMA2_PD */
123					 0xff
124					 0xfa
125					 0x7f /* No ESPI_PD */
126					 0xff
127					 0xcf>; /* No FIU_PD */
128		};
129
130		/* Wake-up input source mapping for GPIOs in npcx4 series */
131		gpio0: gpio@40081000 {
132			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
133				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
134
135			lvol-maps = <&lvol_io00 &lvol_io01 &lvol_io02 &lvol_io03
136				     &lvol_io04 &lvol_io05 &lvol_io06 &lvol_io07>;
137		};
138
139		gpio1: gpio@40083000 {
140			wui-maps = <&wui_io10 &wui_io11 &wui_io12 &wui_io13
141				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
142
143			lvol-maps = <&lvol_io10 &lvol_io11 &lvol_none &lvol_io13
144				     &lvol_io14 &lvol_io15 &lvol_io16 &lvol_io17>;
145		};
146
147		gpio2: gpio@40085000 {
148			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
149				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
150
151			lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23
152				     &lvol_none &lvol_none &lvol_none &lvol_none>;
153		};
154
155		gpio3: gpio@40087000 {
156			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
157				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
158
159			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
160				     &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>;
161		};
162
163		gpio4: gpio@40089000 {
164			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
165				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
166
167			lvol-maps = <&lvol_io40 &lvol_io41 &lvol_io42 &lvol_io43
168				     &lvol_io44 &lvol_io45 &lvol_none &lvol_none>;
169		};
170
171		gpio5: gpio@4008b000 {
172			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
173				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
174
175			lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
176				     &lvol_none &lvol_none &lvol_none &lvol_none>;
177		};
178
179		gpio6: gpio@4008d000 {
180			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
181				    &wui_io64 &wui_none &wui_io66 &wui_io67>;
182
183			lvol-maps = <&lvol_io60 &lvol_io61 &lvol_io62 &lvol_io63
184				     &lvol_io64 &lvol_none &lvol_io66 &lvol_io67>;
185		};
186
187		gpio7: gpio@4008f000 {
188			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
189				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
190
191			lvol-maps = <&lvol_io70 &lvol_none &lvol_io72 &lvol_io73
192				     &lvol_io74 &lvol_io75 &lvol_io76 &lvol_none>;
193		};
194
195		gpio8: gpio@40091000 {
196			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
197				    &wui_none &wui_none &wui_none &wui_io87>;
198
199			lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_io83
200				     &lvol_none &lvol_none &lvol_none &lvol_io87>;
201		};
202
203		gpio9: gpio@40093000 {
204			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
205				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
206
207			lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
208				     &lvol_none &lvol_none &lvol_none &lvol_none>;
209		};
210
211		gpioa: gpio@40095000 {
212			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
213				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
214
215			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
216				     &lvol_none &lvol_none &lvol_none &lvol_none>;
217		};
218
219		gpiob: gpio@40097000 {
220			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
221				    &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>;
222
223			lvol-maps = <&lvol_none &lvol_iob1 &lvol_iob2 &lvol_iob3
224				     &lvol_iob4 &lvol_iob5 &lvol_iob6 &lvol_iob7>;
225		};
226
227		gpioc: gpio@40099000 {
228			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
229				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
230
231			lvol-maps = <&lvol_ioc0 &lvol_ioc1 &lvol_ioc2 &lvol_ioc3
232				     &lvol_ioc4 &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>;
233		};
234
235		gpiod: gpio@4009b000 {
236			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
237				    &wui_iod4 &wui_iod5 &wui_iod6 &wui_none>;
238
239			lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_iod2 &lvol_iod3
240				     &lvol_iod4 &lvol_iod5 &lvol_iod6 &lvol_none>;
241		};
242
243		gpioe: gpio@4009d000 {
244			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
245				    &wui_ioe4 &wui_ioe5 &wui_none &wui_ioe7>;
246
247			lvol-maps = <&lvol_ioe0 &lvol_ioe1 &lvol_ioe2 &lvol_ioe3
248				     &lvol_ioe4 &lvol_ioe5 &lvol_none &lvol_ioe7>;
249		};
250
251		gpiof: gpio@4009f000 {
252			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
253				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
254
255			lvol-maps = <&lvol_iof0 &lvol_iof1 &lvol_iof2 &lvol_iof3
256				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
257		};
258
259		/* ADC0 comparator configuration in npcx4 series */
260		adc0: adc@400d1000 {
261			channel-count = <26>;
262			threshold-count = <6>;
263		};
264
265		/* ADC1 which reference voltage is AVCC */
266		adc1: adc@400d5000 {
267			compatible = "nuvoton,npcx-adc";
268			#io-channel-cells = <1>;
269			reg = <0x400d5000 0x2000>;
270			interrupts = <22 3>;
271			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>;
272			vref-mv = <3300>;
273			channel-count = <26>;
274			threshold-count = <6>;
275			status = "disabled";
276		};
277
278		/* FIU0 configuration in npcx4 series */
279		qspi_fiu0: quadspi@40020000 {
280			clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 5>;
281		};
282
283		/* FIU1 configuration in npcx4 series */
284		qspi_fiu1: quadspi@40021000 {
285			compatible = "nuvoton,npcx-fiu-qspi";
286			#address-cells = <1>;
287			#size-cells = <0>;
288			reg = <0x40021000 0x1000>;
289			clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 6>;
290		};
291
292		sha0: sha@13c {
293			compatible = "nuvoton,npcx-sha";
294			reg = <0x13c 0x3c>;
295			context-buffer-size = <228>;
296			status = "disabled";
297		};
298	};
299
300	soc-if {
301		i2c4_0: io_i2c_ctrl4_port0 {
302			compatible = "nuvoton,npcx-i2c-port";
303			#address-cells = <1>;
304			#size-cells = <0>;
305			port = <0x40>;
306			controller = <&i2c_ctrl4>;
307			status = "disabled";
308		};
309
310		i2c7_1: io_i2c_ctrl7_port1 {
311			compatible = "nuvoton,npcx-i2c-port";
312			#address-cells = <1>;
313			#size-cells = <0>;
314			port = <0x71>;
315			controller = <&i2c_ctrl7>;
316			status = "disabled";
317		};
318	};
319
320	soc-id {
321		chip-id = <0x0a>;
322		revision-reg = <0x0000FFFC 4>;
323	};
324};
325