1/* 2 * Copyright (c) 2021 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9/* Macros for device tree declarations of npcx soc family */ 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/clock/npcx_clock.h> 12#include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15#include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h> 16#include <zephyr/dt-bindings/pwm/pwm.h> 17#include <zephyr/dt-bindings/sensor/npcx_tach.h> 18#include <freq.h> 19 20/ { 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <0>; 29 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>; 30 }; 31 32 power-states { 33 suspend_to_idle0: suspend-to-idle0 { 34 compatible = "zephyr,power-state"; 35 power-state-name = "suspend-to-idle"; 36 substate-id = <0>; 37 min-residency-us = <1000>; 38 }; 39 40 suspend_to_idle1: suspend-to-idle1 { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <1>; 44 min-residency-us = <201000>; 45 }; 46 }; 47 }; 48 49 def-io-conf-list { 50 compatible = "nuvoton,npcx-pinctrl-def"; 51 /* Change default functional pads to GPIOs 52 * no_spip - PIN95.97.A1.A3 53 * no_fpip - PIN96.A0.A2.A4 - Internal flash only 54 * no_pwrgd - PIN72 55 * no_lpc_espi - PIN46.47.51.52.53.54.55.57 56 * no_peci_en - PIN81 57 * npsl_in1_sl - PIND2 58 * npsl_in2_sl - PIN00 59 * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 60 * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. 61 * 82.83.03.B1 62 */ 63 pinmux = <>; 64 }; 65 66 /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. 67 * Then, the user can override the pin control options at the board level. 68 */ 69 pinctrl: pinctrl { 70 compatible = "nuvoton,npcx-pinctrl"; 71 status = "okay"; 72 }; 73 74 /* Dummy node of IOs that have leakage current. The user can override 75 * 'leak-gpios' prop. at board DT file to save more power consumption. 76 */ 77 power_leakage_io: power-leakage-io { 78 compatible = "nuvoton,npcx-leakage-io"; 79 status = "okay"; 80 }; 81 82 soc { 83 bbram: bb-ram@400af000 { 84 compatible = "nuvoton,npcx-bbram"; 85 reg = <0x400af000 0x80 86 0x400af100 0x1>; 87 reg-names = "memory", "status"; 88 }; 89 90 pcc: clock-controller@4000d000 { 91 compatible = "nuvoton,npcx-pcc"; 92 /* Cells for bus type, clock control reg and bit */ 93 #clock-cells = <3>; 94 /* First reg region is Power Management Controller */ 95 /* Second reg region is Core Domain Clock Generator */ 96 reg = <0x4000d000 0x2000 97 0x400b5000 0x2000>; 98 reg-names = "pmc", "cdcg"; 99 }; 100 101 scfg: scfg@400c3000 { 102 compatible = "nuvoton,npcx-scfg"; 103 /* First reg region is System Configuration Device */ 104 /* Second reg region is Debugger Interface Device */ 105 /* Third reg region is System Glue Device */ 106 reg = <0x400c3000 0x70 107 0x400c3070 0x30 108 0x400a5000 0x2000>; 109 reg-names = "scfg", "dbg", "glue"; 110 #alt-cells = <3>; 111 #lvol-cells = <2>; 112 }; 113 114 mdc: mdc@4000c000 { 115 compatible = "syscon"; 116 reg = <0x4000c000 0xa>; 117 reg-io-width = <1>; 118 }; 119 120 mdc_header: mdc@4000c00a { 121 compatible = "syscon"; 122 reg = <0x4000c00a 0x4>; 123 reg-io-width = <2>; 124 }; 125 126 miwu0: miwu@400bb000 { 127 compatible = "nuvoton,npcx-miwu"; 128 reg = <0x400bb000 0x2000>; 129 index = <0>; 130 #miwu-cells = <2>; 131 }; 132 133 miwu1: miwu@400bd000 { 134 compatible = "nuvoton,npcx-miwu"; 135 reg = <0x400bd000 0x2000>; 136 index = <1>; 137 #miwu-cells = <2>; 138 }; 139 140 miwu2: miwu@400bf000 { 141 compatible = "nuvoton,npcx-miwu"; 142 reg = <0x400bf000 0x2000>; 143 index = <2>; 144 #miwu-cells = <2>; 145 }; 146 147 gpio0: gpio@40081000 { 148 compatible = "nuvoton,npcx-gpio"; 149 reg = <0x40081000 0x2000>; 150 gpio-controller; 151 index = <0x0>; 152 #gpio-cells=<2>; 153 }; 154 155 gpio1: gpio@40083000 { 156 compatible = "nuvoton,npcx-gpio"; 157 reg = <0x40083000 0x2000>; 158 gpio-controller; 159 index = <0x1>; 160 #gpio-cells=<2>; 161 }; 162 163 gpio2: gpio@40085000 { 164 compatible = "nuvoton,npcx-gpio"; 165 reg = <0x40085000 0x2000>; 166 gpio-controller; 167 index = <0x2>; 168 #gpio-cells=<2>; 169 }; 170 171 gpio3: gpio@40087000 { 172 compatible = "nuvoton,npcx-gpio"; 173 reg = <0x40087000 0x2000>; 174 gpio-controller; 175 index = <0x3>; 176 #gpio-cells=<2>; 177 }; 178 179 gpio4: gpio@40089000 { 180 compatible = "nuvoton,npcx-gpio"; 181 reg = <0x40089000 0x2000>; 182 gpio-controller; 183 index = <0x4>; 184 #gpio-cells=<2>; 185 }; 186 187 gpio5: gpio@4008b000 { 188 compatible = "nuvoton,npcx-gpio"; 189 reg = <0x4008b000 0x2000>; 190 gpio-controller; 191 index = <0x5>; 192 #gpio-cells=<2>; 193 }; 194 195 gpio6: gpio@4008d000 { 196 compatible = "nuvoton,npcx-gpio"; 197 reg = <0x4008d000 0x2000>; 198 gpio-controller; 199 index = <0x6>; 200 #gpio-cells=<2>; 201 }; 202 203 gpio7: gpio@4008f000 { 204 compatible = "nuvoton,npcx-gpio"; 205 reg = <0x4008f000 0x2000>; 206 gpio-controller; 207 index = <0x7>; 208 #gpio-cells=<2>; 209 }; 210 211 gpio8: gpio@40091000 { 212 compatible = "nuvoton,npcx-gpio"; 213 reg = <0x40091000 0x2000>; 214 gpio-controller; 215 index = <0x8>; 216 #gpio-cells=<2>; 217 }; 218 219 gpio9: gpio@40093000 { 220 compatible = "nuvoton,npcx-gpio"; 221 reg = <0x40093000 0x2000>; 222 gpio-controller; 223 index = <0x9>; 224 #gpio-cells=<2>; 225 }; 226 227 gpioa: gpio@40095000 { 228 compatible = "nuvoton,npcx-gpio"; 229 reg = <0x40095000 0x2000>; 230 gpio-controller; 231 index = <0xA>; 232 #gpio-cells=<2>; 233 }; 234 235 gpiob: gpio@40097000 { 236 compatible = "nuvoton,npcx-gpio"; 237 reg = <0x40097000 0x2000>; 238 gpio-controller; 239 index = <0xB>; 240 #gpio-cells=<2>; 241 }; 242 243 gpioc: gpio@40099000 { 244 compatible = "nuvoton,npcx-gpio"; 245 reg = <0x40099000 0x2000>; 246 gpio-controller; 247 index = <0xC>; 248 #gpio-cells=<2>; 249 }; 250 251 gpiod: gpio@4009b000 { 252 compatible = "nuvoton,npcx-gpio"; 253 reg = <0x4009b000 0x2000>; 254 gpio-controller; 255 index = <0xD>; 256 #gpio-cells=<2>; 257 }; 258 259 gpioe: gpio@4009d000 { 260 compatible = "nuvoton,npcx-gpio"; 261 reg = <0x4009d000 0x2000>; 262 gpio-controller; 263 index = <0xE>; 264 #gpio-cells=<2>; 265 }; 266 267 gpiof: gpio@4009f000 { 268 compatible = "nuvoton,npcx-gpio"; 269 reg = <0x4009f000 0x2000>; 270 gpio-controller; 271 index = <0xF>; 272 #gpio-cells=<2>; 273 }; 274 275 pwm0: pwm@40080000 { 276 compatible = "nuvoton,npcx-pwm"; 277 reg = <0x40080000 0x2000>; 278 pwm-channel = <0>; 279 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; 280 #pwm-cells = <3>; 281 status = "disabled"; 282 }; 283 284 pwm1: pwm@40082000 { 285 compatible = "nuvoton,npcx-pwm"; 286 reg = <0x40082000 0x2000>; 287 pwm-channel = <1>; 288 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; 289 #pwm-cells = <3>; 290 status = "disabled"; 291 }; 292 293 pwm2: pwm@40084000 { 294 compatible = "nuvoton,npcx-pwm"; 295 reg = <0x40084000 0x2000>; 296 pwm-channel = <2>; 297 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; 298 #pwm-cells = <3>; 299 status = "disabled"; 300 }; 301 302 pwm3: pwm@40086000 { 303 compatible = "nuvoton,npcx-pwm"; 304 reg = <0x40086000 0x2000>; 305 pwm-channel = <3>; 306 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; 307 #pwm-cells = <3>; 308 status = "disabled"; 309 }; 310 311 pwm4: pwm@40088000 { 312 compatible = "nuvoton,npcx-pwm"; 313 reg = <0x40088000 0x2000>; 314 pwm-channel = <4>; 315 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; 316 #pwm-cells = <3>; 317 status = "disabled"; 318 }; 319 320 pwm5: pwm@4008a000 { 321 compatible = "nuvoton,npcx-pwm"; 322 reg = <0x4008a000 0x2000>; 323 pwm-channel = <5>; 324 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; 325 #pwm-cells = <3>; 326 status = "disabled"; 327 }; 328 329 pwm6: pwm@4008c000 { 330 compatible = "nuvoton,npcx-pwm"; 331 reg = <0x4008c000 0x2000>; 332 pwm-channel = <6>; 333 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; 334 #pwm-cells = <3>; 335 status = "disabled"; 336 }; 337 338 pwm7: pwm@4008e000 { 339 compatible = "nuvoton,npcx-pwm"; 340 reg = <0x4008e000 0x2000>; 341 pwm-channel = <7>; 342 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; 343 #pwm-cells = <3>; 344 status = "disabled"; 345 }; 346 347 adc0: adc@400d1000 { 348 compatible = "nuvoton,npcx-adc"; 349 #io-channel-cells = <1>; 350 reg = <0x400d1000 0x2000>; 351 interrupts = <10 3>; 352 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; 353 vref-mv = <2816>; 354 status = "disabled"; 355 }; 356 357 twd0: watchdog@400d8000 { 358 compatible = "nuvoton,npcx-watchdog"; 359 reg = <0x400d8000 0x2000>; 360 t0-out = <&wui_t0out>; 361 }; 362 363 espi0: espi@4000a000 { 364 compatible = "nuvoton,npcx-espi"; 365 reg = <0x4000a000 0x2000>; 366 interrupts = <18 3>; /* Interrupt for eSPI Bus */ 367 368 /* clocks for eSPI modules */ 369 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; 370 /* WUI maps for eSPI signals */ 371 espi-rst-wui = <&wui_espi_rst>; 372 373 #address-cells = <1>; 374 #size-cells = <0>; 375 #vw-cells = <3>; 376 status = "disabled"; 377 }; 378 379 shi0: shi@4000f000 { 380 compatible = "nuvoton,npcx-shi"; 381 reg = <0x4000f000 0x120>; 382 interrupts = <18 1>; 383 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; 384 status = "disabled"; 385 buffer-rx-size = <128>; 386 buffer-tx-size = <128>; 387 }; 388 389 host_sub: lpc@400c1000 { 390 compatible = "nuvoton,npcx-host-sub"; 391 /* host sub-module register address & size */ 392 reg = <0x400c1000 0x2000 393 0x40010000 0x2000 394 0x4000e000 0x2000 395 0x400c7000 0x2000 396 0x400c9000 0x2000 397 0x400cb000 0x2000>; 398 reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", 399 "pm_hcmd"; 400 401 /* host sub-module IRQ and priority */ 402 interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ 403 <56 3>, /* KBC Output-Buf-Empty (OBE) */ 404 <26 3>, /* PMCH Input-Buf-Full (IBF) */ 405 <3 3>, /* PMCH Output-Buf-Empty (OBE) */ 406 <6 3>; /* Port80 FIFO Not Empty */ 407 interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", 408 "pmch_obe", "p80_fifo"; 409 410 /* WUI map for accessing host sub-modules */ 411 host-acc-wui = <&wui_host_acc>; 412 413 /* clocks for host sub-modules */ 414 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, 415 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, 416 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, 417 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, 418 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; 419 }; 420 421 /* I2c Controllers - Do not use them as i2c node directly */ 422 i2c_ctrl0: i2c@40009000 { 423 compatible = "nuvoton,npcx-i2c-ctrl"; 424 reg = <0x40009000 0x1000>; 425 interrupts = <13 3>; 426 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; 427 status = "disabled"; 428 }; 429 430 i2c_ctrl1: i2c@4000b000 { 431 compatible = "nuvoton,npcx-i2c-ctrl"; 432 reg = <0x4000b000 0x1000>; 433 interrupts = <14 3>; 434 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; 435 status = "disabled"; 436 }; 437 438 i2c_ctrl2: i2c@400c0000 { 439 compatible = "nuvoton,npcx-i2c-ctrl"; 440 reg = <0x400c0000 0x1000>; 441 interrupts = <36 3>; 442 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; 443 status = "disabled"; 444 }; 445 446 i2c_ctrl3: i2c@400c2000 { 447 compatible = "nuvoton,npcx-i2c-ctrl"; 448 reg = <0x400c2000 0x1000>; 449 interrupts = <37 3>; 450 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; 451 status = "disabled"; 452 }; 453 454 i2c_ctrl4: i2c@40008000 { 455 compatible = "nuvoton,npcx-i2c-ctrl"; 456 reg = <0x40008000 0x1000>; 457 interrupts = <19 3>; 458 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; 459 status = "disabled"; 460 }; 461 462 i2c_ctrl5: i2c@40017000 { 463 compatible = "nuvoton,npcx-i2c-ctrl"; 464 reg = <0x40017000 0x1000>; 465 interrupts = <20 3>; 466 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; 467 status = "disabled"; 468 }; 469 470 i2c_ctrl6: i2c@40018000 { 471 compatible = "nuvoton,npcx-i2c-ctrl"; 472 reg = <0x40018000 0x1000>; 473 interrupts = <16 3>; 474 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; 475 status = "disabled"; 476 }; 477 478 i2c_ctrl7: i2c@40019000 { 479 compatible = "nuvoton,npcx-i2c-ctrl"; 480 reg = <0x40019000 0x1000>; 481 interrupts = <8 3>; 482 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; 483 status = "disabled"; 484 }; 485 486 tach1: tach@400e1000 { 487 compatible = "nuvoton,npcx-tach"; 488 reg = <0x400e1000 0x2000>; 489 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; 490 status = "disabled"; 491 }; 492 493 tach2: tach@400e3000 { 494 compatible = "nuvoton,npcx-tach"; 495 reg = <0x400e3000 0x2000>; 496 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; 497 status = "disabled"; 498 }; 499 500 ps2_ctrl0: ps2@400b1000 { 501 compatible = "nuvoton,npcx-ps2-ctrl"; 502 reg = <0x400b1000 0x1000>; 503 interrupts = <21 4>; 504 clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; 505 506 /* PS2 Channels - Please use them as PS2 node */ 507 ps2_channel0: io_ps2_channel0 { 508 compatible = "nuvoton,npcx-ps2-channel"; 509 channel = <0x00>; 510 status = "disabled"; 511 }; 512 513 ps2_channel1: io_ps2_channel1 { 514 compatible = "nuvoton,npcx-ps2-channel"; 515 channel = <0x01>; 516 status = "disabled"; 517 }; 518 519 ps2_channel2: io_ps2_channel2 { 520 compatible = "nuvoton,npcx-ps2-channel"; 521 channel = <0x02>; 522 status = "disabled"; 523 }; 524 525 ps2_channel3: io_ps2_channel3 { 526 compatible = "nuvoton,npcx-ps2-channel"; 527 channel = <0x03>; 528 status = "disabled"; 529 }; 530 }; 531 532 /* Dedicated Quad-SPI interface to access SPI flashes */ 533 qspi_fiu0: quadspi@40020000 { 534 compatible = "nuvoton,npcx-fiu-qspi"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x40020000 0x2000>; 538 }; 539 540 peci0: peci@400d4000 { 541 compatible = "nuvoton,npcx-peci"; 542 reg = <0x400d4000 0x1000>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 interrupts = <4 4>; 546 clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; 547 status = "disabled"; 548 }; 549 550 kbd: kbd@400a3000 { 551 compatible = "nuvoton,npcx-kbd"; 552 reg = <0x400a3000 0x2000>; 553 interrupts = <49 4>; 554 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; 555 wui-maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26 556 &wui_io25 &wui_io24 &wui_io23 &wui_io22>; 557 status = "disabled"; 558 }; 559 }; 560 561 soc-if { 562 /* Soc specific peripheral interface phandles which don't contain 563 * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you 564 * want to switch the interface from io to specific peripheral. 565 */ 566 host_uart: io_host_uart { 567 compatible = "nuvoton,npcx-host-uart"; 568 status = "disabled"; 569 }; 570 571 i2c0_0: io_i2c_ctrl0_port0 { 572 compatible = "nuvoton,npcx-i2c-port"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 port = <0x00>; 576 controller = <&i2c_ctrl0>; 577 status = "disabled"; 578 }; 579 580 i2c1_0: io_i2c_ctrl1_port0 { 581 compatible = "nuvoton,npcx-i2c-port"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 port = <0x10>; 585 controller = <&i2c_ctrl1>; 586 status = "disabled"; 587 }; 588 589 i2c2_0: io_i2c_ctrl2_port0 { 590 compatible = "nuvoton,npcx-i2c-port"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 port = <0x20>; 594 controller = <&i2c_ctrl2>; 595 status = "disabled"; 596 }; 597 598 i2c3_0: io_i2c_ctrl3_port0 { 599 compatible = "nuvoton,npcx-i2c-port"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 port = <0x30>; 603 controller = <&i2c_ctrl3>; 604 status = "disabled"; 605 }; 606 607 i2c4_1: io_i2c_ctrl4_port1 { 608 compatible = "nuvoton,npcx-i2c-port"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 port = <0x41>; 612 controller = <&i2c_ctrl4>; 613 status = "disabled"; 614 }; 615 616 i2c5_0: io_i2c_ctrl5_port0 { 617 compatible = "nuvoton,npcx-i2c-port"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 port = <0x50>; 621 controller = <&i2c_ctrl5>; 622 status = "disabled"; 623 }; 624 625 i2c5_1: io_i2c_ctrl5_port1 { 626 compatible = "nuvoton,npcx-i2c-port"; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 port = <0x51>; 630 controller = <&i2c_ctrl5>; 631 status = "disabled"; 632 }; 633 634 i2c6_0: io_i2c_ctrl6_port0 { 635 compatible = "nuvoton,npcx-i2c-port"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 port = <0x60>; 639 controller = <&i2c_ctrl6>; 640 status = "disabled"; 641 }; 642 643 i2c6_1: io_i2c_ctrl6_port1 { 644 compatible = "nuvoton,npcx-i2c-port"; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 port = <0x61>; 648 controller = <&i2c_ctrl6>; 649 status = "disabled"; 650 }; 651 652 i2c7_0: io_i2c_ctrl7_port0 { 653 compatible = "nuvoton,npcx-i2c-port"; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 port = <0x70>; 657 controller = <&i2c_ctrl7>; 658 status = "disabled"; 659 }; 660 661 power_ctrl_psl: power-ctrl-psl { 662 compatible = "nuvoton,npcx-power-psl"; 663 status = "disabled"; 664 }; 665 }; 666 667 soc-id { 668 compatible = "nuvoton,npcx-soc-id"; 669 family-id = <0x20>; 670 }; 671 672 booter-variant { 673 compatible = "nuvoton,npcx-booter-variant"; 674 }; 675}; 676 677&nvic { 678 arm,num-irq-priority-bits = <3>; 679}; 680
