1/*
2 * Copyright (c) 2020 Linumiz
3 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-m4f";
20			reg = <0>;
21		};
22	};
23
24	flash_controller: flash_controller@58001000 {
25		compatible = "infineon,xmc4xxx-flash-controller";
26		reg = <0x58001000 0x1400>;
27		#address-cells = <1>;
28		#size-cells = <1>;
29		flash0: flash@c000000 {
30			compatible = "infineon,xmc4xxx-nv-flash","soc-nv-flash";
31			write-block-size = <256>;
32		};
33	};
34
35	sysclk: system-clock {
36		compatible = "fixed-clock";
37		clock-frequency = <120000000>;
38		#clock-cells = <0>;
39	};
40
41	soc {
42		intc: eru@40044000 {
43			compatible = "infineon,xmc4xxx-intc";
44			reg = <0x40044000 0xff>, <0x50004800 0xff>;
45			/* naming order is intentional. eru1 maps to a lower address than eru0 */
46			reg-names = "eru1", "eru0";
47			interrupts = <1 1>, <2 1>, <3 1>, <4 1>, <5 1>, <6 1>, <7 1>, <8 1>;
48			interrupt-names = "eru0sr0", "eru0sr1", "eru0sr2", "eru0sr3",
49					"eru1sr0", "eru1sr1", "eru1sr2", "eru1sr3";
50		};
51
52		pinctrl: pinctrl@48028000 {
53			compatible = "infineon,xmc4xxx-pinctrl";
54			reg = <0x48028000 0x1000>;
55			#address-cells = <1>;
56			#size-cells = <1>;
57
58			gpio0: gpio@48028000 {
59				compatible = "infineon,xmc4xxx-gpio";
60				gpio-controller;
61				#gpio-cells = <2>;
62				reg = <0x48028000 0x100>;
63				status = "disabled";
64			};
65
66			gpio1: gpio@48028100 {
67				compatible = "infineon,xmc4xxx-gpio";
68				gpio-controller;
69				#gpio-cells = <2>;
70				reg = <0x48028100 0x100>;
71				status = "disabled";
72			};
73
74			gpio2: gpio@48028200 {
75				compatible = "infineon,xmc4xxx-gpio";
76				gpio-controller;
77				#gpio-cells = <2>;
78				reg = <0x48028200 0x100>;
79				status = "disabled";
80			};
81
82			gpio14: gpio@48028e00 {
83				compatible = "infineon,xmc4xxx-gpio";
84				gpio-controller;
85				#gpio-cells = <2>;
86				reg = <0x48028e00 0x100>;
87				status = "disabled";
88			};
89
90			gpio15: gpio@48028f00 {
91				compatible = "infineon,xmc4xxx-gpio";
92				gpio-controller;
93				#gpio-cells = <2>;
94				reg = <0x48028f00 0x100>;
95				status = "disabled";
96			};
97		};
98
99		dma0: dma0@50014000{
100			compatible = "infineon,xmc4xxx-dma";
101			reg = <0x50014000 0x2bc>;
102			interrupts = <105 1>;
103			dma-channels = <8>;
104			#dma-cells = <3>;
105			status = "disabled";
106		};
107
108		dma1: dma1@50018000 {
109			compatible = "infineon,xmc4xxx-dma";
110			reg = <0x50018000 0x15c>;
111			interrupts = <110 1>;
112			dma-channels = <4>;
113			#dma-cells = <3>;
114			status = "disabled";
115		};
116
117		usic0ch0: usic@40030000 {
118			reg = <0x40030000 0x1ff>;
119			clocks = <&sysclk>;
120			status = "disabled";
121		};
122
123		usic0ch1: usic@40030200 {
124			reg = <0x40030200 0x1ff>;
125			clocks = <&sysclk>;
126			status = "disabled";
127		};
128
129		usic1ch0: usic@48020000 {
130			reg = <0x48020000 0x1ff>;
131			clocks = <&sysclk>;
132			status = "disabled";
133		};
134
135		usic1ch1: usic@48020200 {
136			reg = <0x48020200 0x1ff>;
137			clocks = <&sysclk>;
138			status = "disabled";
139		};
140
141		usic2ch0: usic@48024000 {
142			reg = <0x48024000 0x1ff>;
143			clocks = <&sysclk>;
144			status = "disabled";
145		};
146
147		usic2ch1: usic@48024200 {
148			reg = <0x48024200 0x1ff>;
149			clocks = <&sysclk>;
150			status = "disabled";
151		};
152
153		adc0: adc@40004400 {
154			compatible = "infineon,xmc4xxx-adc";
155			reg = <0x40004400 0x400>;
156			interrupts = <18 62>;
157			#io-channel-cells = <1>;
158			status = "disabled";
159		};
160
161		adc1: adc@40004800 {
162			compatible = "infineon,xmc4xxx-adc";
163			reg = <0x40004800 0x400>;
164			interrupts = <22 62>;
165			#io-channel-cells = <1>;
166			status = "disabled";
167		};
168
169		adc2: adc@40004c00 {
170			compatible = "infineon,xmc4xxx-adc";
171			reg = <0x40004C00 0x400>;
172			interrupts = <26 62>;
173			#io-channel-cells = <1>;
174			status = "disabled";
175		};
176
177		adc3: adc@40005000 {
178			compatible = "infineon,xmc4xxx-adc";
179			reg = <0x40005000 0x400>;
180			interrupts = <30 62>;
181			#io-channel-cells = <1>;
182			status = "disabled";
183		};
184
185		die_temp: die_temp@5000408c {
186			reg = <0x5000408c 0x8>;
187			compatible = "infineon,xmc4xxx-temp";
188			status = "disabled";
189		};
190
191		pwm_ccu40: ccu40@4000c000 {
192			compatible = "infineon,xmc4xxx-ccu4-pwm";
193			reg = <0x4000c000 0x4000>;
194			#pwm-cells = <3>;
195			status = "disabled";
196		};
197
198		pwm_ccu41: ccu41@40010000 {
199			compatible = "infineon,xmc4xxx-ccu4-pwm";
200			reg = <0x40010000 0x4000>;
201			#pwm-cells = <3>;
202			status = "disabled";
203		};
204
205		pwm_ccu42: ccu42@40014000 {
206			compatible = "infineon,xmc4xxx-ccu4-pwm";
207			reg = <0x40014000 0x4000>;
208			#pwm-cells = <3>;
209			status = "disabled";
210		};
211
212		pwm_ccu43: ccu43@48004000 {
213			compatible = "infineon,xmc4xxx-ccu4-pwm";
214			reg = <0x48004000 0x4000>;
215			#pwm-cells = <3>;
216			status = "disabled";
217		};
218
219		pwm_ccu80: ccu80@40020000 {
220			compatible = "infineon,xmc4xxx-ccu8-pwm";
221			reg = <0x40020000 0x4000>;
222			#pwm-cells = <3>;
223			status = "disabled";
224		};
225
226		pwm_ccu81: ccu81@40024000 {
227			compatible = "infineon,xmc4xxx-ccu8-pwm";
228			reg = <0x40024000 0x4000>;
229			#pwm-cells = <3>;
230			status = "disabled";
231		};
232	};
233};
234
235&nvic {
236	arm,num-irq-priority-bits = <6>;
237};
238