1/*
2 * Copyright (c) 2023 Schlumberger
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <infineon/xmc4xxx.dtsi>
9
10/ {
11	psram1: memory@1ffe8000 {
12		compatible = "mmio-sram";
13		reg = <0x1ffe8000 DT_SIZE_K(96)>;
14	};
15
16	dsram1: memory@20000000 {
17		compatible = "mmio-sram";
18		reg = <0x20000000 DT_SIZE_K(128)>;
19	};
20
21	dsram2: memory@20020000 {
22		compatible = "mmio-sram";
23		reg = <0x20020000 DT_SIZE_K(128)>;
24	};
25};
26
27&flash0 {
28	reg = <0xc000000 DT_SIZE_M(2)>;
29	pages_layout: pages_layout {
30		pages_layout_16k: pages_layout_16k {
31			pages-count = <8>;
32			pages-size = <DT_SIZE_K(16)>;
33		};
34		pages_layout_128k: pages_layout_128k {
35			pages-count = <1>;
36			pages-size = <DT_SIZE_K(128)>;
37		};
38		pages_layout_256k: pages_layout_256k {
39			pages-count = <7>;
40			pages-size = <DT_SIZE_K(256)>;
41		};
42	};
43};
44
45&gpio0 {
46	ngpios = <16>;
47};
48
49&gpio1 {
50	ngpios = <16>;
51};
52
53&gpio2 {
54	ngpios = <16>;
55};
56
57&gpio14 {
58	ngpios = <16>;
59	gpio-reserved-ranges = <10 2>;
60};
61
62&gpio15 {
63	ngpios = <16>;
64	gpio-reserved-ranges = <0 2>, <10 2>;
65};
66
67&pinctrl {
68	gpio3: gpio@48028300 {
69		compatible = "infineon,xmc4xxx-gpio";
70		gpio-controller;
71		#gpio-cells = <2>;
72		reg = <0x48028300 0x100>;
73		ngpios = <16>;
74		status = "disabled";
75	};
76
77	gpio4: gpio@48028400 {
78		compatible = "infineon,xmc4xxx-gpio";
79		gpio-controller;
80		#gpio-cells = <2>;
81		reg = <0x48028400 0x100>;
82		ngpios = <8>;
83		status = "disabled";
84	};
85
86	gpio5: gpio@48028500 {
87		compatible = "infineon,xmc4xxx-gpio";
88		gpio-controller;
89		#gpio-cells = <2>;
90		reg = <0x48028500 0x100>;
91		ngpios = <12>;
92		status = "disabled";
93	};
94
95	gpio6: gpio@48028600 {
96		compatible = "infineon,xmc4xxx-gpio";
97		gpio-controller;
98		#gpio-cells = <2>;
99		reg = <0x48028600 0x100>;
100		ngpios = <7>;
101		status = "disabled";
102	};
103};
104