1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_03.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40310080; // gpio_prt1
15		/delete-node/ gpio@40310200; // gpio_prt4
16		/delete-node/ gpio@40310680; // gpio_prt13
17
18		pinctrl: pinctrl@40300000 {
19			/* scb_i2c_scl */
20			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
21				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
22			};
23			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
24				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
25			};
26			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
27				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
28			};
29			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
30				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
31			};
32			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
33				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
34			};
35			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
36				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
37			};
38			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
39				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
40			};
41			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
42				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
43			};
44			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
45				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
46			};
47			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
48				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
49			};
50
51			/* scb_i2c_sda */
52			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
53				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
54			};
55			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
56				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
57			};
58			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
59				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
60			};
61			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
62				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
63			};
64			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
65				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
66			};
67			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
68				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
69			};
70			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
71				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
72			};
73			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
74				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
75			};
76			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
77				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
78			};
79			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
80				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
81			};
82
83			/* scb_uart_cts */
84			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
85				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
86			};
87			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
88				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
89			};
90			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
91				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
92			};
93			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
94				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
95			};
96			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
97				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
98			};
99			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
100				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
101			};
102			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
103				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
104			};
105
106			/* scb_uart_rts */
107			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
108				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
109			};
110			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
111				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
112			};
113			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
114				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
115			};
116			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
117				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
118			};
119			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
120				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
121			};
122			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
123				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
124			};
125			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
126				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
127			};
128
129			/* scb_uart_rx */
130			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
131				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
132			};
133			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
134				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
135			};
136			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
137				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
138			};
139			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
140				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
141			};
142			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
143				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
144			};
145			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
146				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
147			};
148			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
149				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
150			};
151			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
152				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
153			};
154			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
155				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
156			};
157
158			/* scb_uart_tx */
159			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
160				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
161			};
162			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
163				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
164			};
165			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
166				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
167			};
168			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
169				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
170			};
171			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
172				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
173			};
174			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
175				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
176			};
177			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
178				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
179			};
180			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
181				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
182			};
183			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
184				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
185			};
186
187		};
188	};
189};
190