1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_02.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40310180; // gpio_prt3
15		/delete-node/ gpio@40310200; // gpio_prt4
16
17		pinctrl: pinctrl@40300000 {
18			/* scb_i2c_scl */
19			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
20				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
21			};
22			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
23				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
24			};
25			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
26				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
27			};
28			/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
29				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
30			};
31			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
32				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
33			};
34			/omit-if-no-ref/ p5_4_scb10_i2c_scl: p5_4_scb10_i2c_scl {
35				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_7)>;
36			};
37			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
38				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
39			};
40			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
41				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
42			};
43			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
44				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
45			};
46			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
47				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
48			};
49			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
50				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
51			};
52			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
53				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
54			};
55			/omit-if-no-ref/ p8_4_scb11_i2c_scl: p8_4_scb11_i2c_scl {
56				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_7)>;
57			};
58			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
59				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
60			};
61			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
62				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
63			};
64			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
65				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
66			};
67			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
68				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
69			};
70			/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
71				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
72			};
73			/omit-if-no-ref/ p13_4_scb12_i2c_scl: p13_4_scb12_i2c_scl {
74				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_7)>;
75			};
76
77			/* scb_i2c_sda */
78			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
79				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
80			};
81			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
82				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
83			};
84			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
85				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
86			};
87			/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
88				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
89			};
90			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
91				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
92			};
93			/omit-if-no-ref/ p5_5_scb10_i2c_sda: p5_5_scb10_i2c_sda {
94				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_7)>;
95			};
96			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
97				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
98			};
99			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
100				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
101			};
102			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
103				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
104			};
105			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
106				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
107			};
108			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
109				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
110			};
111			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
112				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
113			};
114			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
115				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
116			};
117			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
118				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
119			};
120			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
121				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
122			};
123			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
124				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
125			};
126			/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
127				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
128			};
129			/omit-if-no-ref/ p13_5_scb12_i2c_sda: p13_5_scb12_i2c_sda {
130				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_7)>;
131			};
132
133			/* scb_uart_cts */
134			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
135				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
136			};
137			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
138				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
139			};
140			/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
141				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
142			};
143			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
144				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
145			};
146			/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
147				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
148			};
149			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
150				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
151			};
152			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
153				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
154			};
155			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
156				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
157			};
158			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
159				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
160			};
161			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
162				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
163			};
164			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
165				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
166			};
167			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
168				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
169			};
170			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
171				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
172			};
173			/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
174				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
175			};
176			/omit-if-no-ref/ p13_7_scb12_uart_cts: p13_7_scb12_uart_cts {
177				pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_6)>;
178			};
179
180			/* scb_uart_rts */
181			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
182				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
183			};
184			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
185				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
186			};
187			/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
188				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
189			};
190			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
191				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
192			};
193			/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
194				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
195			};
196			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
197				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
198			};
199			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
200				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
201			};
202			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
203				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
204			};
205			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
206				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
207			};
208			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
209				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
210			};
211			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
212				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
213			};
214			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
215				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
216			};
217			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
218				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
219			};
220			/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
221				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
222			};
223			/omit-if-no-ref/ p13_6_scb12_uart_rts: p13_6_scb12_uart_rts {
224				pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_6)>;
225			};
226
227			/* scb_uart_rx */
228			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
229				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
230			};
231			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
232				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
233			};
234			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
235				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
236			};
237			/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
238				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
239			};
240			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
241				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
242			};
243			/omit-if-no-ref/ p5_4_scb10_uart_rx: p5_4_scb10_uart_rx {
244				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_6)>;
245			};
246			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
247				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
248			};
249			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
250				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
251			};
252			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
253				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
254			};
255			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
256				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
257			};
258			/omit-if-no-ref/ p8_4_scb11_uart_rx: p8_4_scb11_uart_rx {
259				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_6)>;
260			};
261			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
262				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
263			};
264			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
265				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
266			};
267			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
268				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
269			};
270			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
271				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
272			};
273			/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
274				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
275			};
276			/omit-if-no-ref/ p13_4_scb12_uart_rx: p13_4_scb12_uart_rx {
277				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_6)>;
278			};
279
280			/* scb_uart_tx */
281			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
282				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
283			};
284			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
285				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
286			};
287			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
288				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
289			};
290			/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
291				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
292			};
293			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
294				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
295			};
296			/omit-if-no-ref/ p5_5_scb10_uart_tx: p5_5_scb10_uart_tx {
297				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_6)>;
298			};
299			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
300				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
301			};
302			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
303				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
304			};
305			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
306				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
307			};
308			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
309				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
310			};
311			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
312				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
313			};
314			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
315				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
316			};
317			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
318				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
319			};
320			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
321				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
322			};
323			/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
324				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
325			};
326			/omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx {
327				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_6)>;
328			};
329
330		};
331	};
332};
333