1 /* 2 * Copyright (c) 2022 Andes Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL 7 #include <zephyr/logging/log.h> 8 LOG_MODULE_REGISTER(spi_atcspi200); 9 10 #include "spi_context.h" 11 #include <zephyr/device.h> 12 #include <zephyr/drivers/spi.h> 13 14 #define REG_IDR 0x00 15 #define REG_TFMAT 0x10 16 #define REG_DIRIO 0x14 17 #define REG_TCTRL 0x20 18 #define REG_CMD 0x24 19 #define REG_ADDR 0x28 20 #define REG_DATA 0x2c 21 #define REG_CTRL 0x30 22 #define REG_STAT 0x34 23 #define REG_INTEN 0x38 24 #define REG_INTST 0x3c 25 #define REG_TIMIN 0x40 26 #define REG_MCTRL 0x50 27 #define REG_SLVST 0x60 28 #define REG_SDCNT 0x64 29 #define REG_CONFIG 0x7c 30 31 #define SPI_BASE (((const struct spi_atcspi200_cfg *)(dev)->config)->base) 32 #define SPI_TFMAT(dev) (SPI_BASE + REG_TFMAT) 33 #define SPI_TCTRL(dev) (SPI_BASE + REG_TCTRL) 34 #define SPI_CMD(dev) (SPI_BASE + REG_CMD) 35 #define SPI_DATA(dev) (SPI_BASE + REG_DATA) 36 #define SPI_CTRL(dev) (SPI_BASE + REG_CTRL) 37 #define SPI_STAT(dev) (SPI_BASE + REG_STAT) 38 #define SPI_INTEN(dev) (SPI_BASE + REG_INTEN) 39 #define SPI_INTST(dev) (SPI_BASE + REG_INTST) 40 #define SPI_TIMIN(dev) (SPI_BASE + REG_TIMIN) 41 #define SPI_CONFIG(dev) (SPI_BASE + REG_CONFIG) 42 43 /* Field mask of SPI transfer format register */ 44 #define TFMAT_DATA_LEN_OFFSET (8) 45 46 #define TFMAT_CPHA_MSK BIT(0) 47 #define TFMAT_CPOL_MSK BIT(1) 48 #define TFMAT_SLVMODE_MSK BIT(2) 49 #define TFMAT_LSB_MSK BIT(3) 50 #define TFMAT_DATA_MERGE_MSK BIT(7) 51 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8) 52 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16) 53 54 /* Field mask of SPI transfer control register */ 55 #define TCTRL_RD_TCNT_OFFSET (0) 56 #define TCTRL_WR_TCNT_OFFSET (12) 57 #define TCTRL_TRNS_MODE_OFFSET (24) 58 59 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12) 60 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24) 61 62 /* Transfer mode */ 63 #define TRNS_MODE_WRITE_READ (0) 64 #define TRNS_MODE_WRITE_ONLY (1) 65 #define TRNS_MODE_READ_ONLY (2) 66 67 /* Field mask of SPI interrupt enable register */ 68 #define IEN_RX_FIFO_MSK BIT(2) 69 #define IEN_TX_FIFO_MSK BIT(3) 70 #define IEN_END_MSK BIT(4) 71 72 /* Field mask of SPI interrupt status register */ 73 #define INTST_RX_FIFO_INT_MSK BIT(2) 74 #define INTST_TX_FIFO_INT_MSK BIT(3) 75 #define INTST_END_INT_MSK BIT(4) 76 77 /* Field mask of SPI config register */ 78 #define CFG_RX_FIFO_SIZE_MSK GENMASK(1, 0) 79 #define CFG_TX_FIFO_SIZE_MSK GENMASK(5, 4) 80 81 /* Field mask of SPI status register */ 82 #define STAT_RX_NUM_MSK GENMASK(12, 8) 83 #define STAT_TX_NUM_MSK GENMASK(20, 16) 84 85 /* Field mask of SPI control register */ 86 #define CTRL_RX_FIFO_RST_OFFSET (1) 87 #define CTRL_TX_FIFO_RST_OFFSET (2) 88 #define CTRL_RX_THRES_OFFSET (8) 89 #define CTRL_TX_THRES_OFFSET (16) 90 91 #define CTRL_RX_FIFO_RST_MSK BIT(1) 92 #define CTRL_TX_FIFO_RST_MSK BIT(2) 93 #define CTRL_RX_THRES_MSK GENMASK(12, 8) 94 #define CTRL_TX_THRES_MSK GENMASK(20, 16) 95 96 /* Field mask of SPI status register */ 97 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0) 98 99 #define SET_MASK(x, msk) sys_write32(sys_read32(x) | msk, x) 100 #define CLR_MASK(x, msk) sys_write32(sys_read32(x) & ~msk, x) 101 102 #define TX_FIFO_THRESHOLD (1) 103 #define RX_FIFO_THRESHOLD (1) 104 #define MAX_TRANSFER_CNT (512) 105 106 #define TX_FIFO_SIZE_SETTING(dev) \ 107 (sys_read32(SPI_CONFIG(dev)) & CFG_TX_FIFO_SIZE_MSK) 108 #define TX_FIFO_SIZE(dev) \ 109 (2 << (TX_FIFO_SIZE_SETTING(dev) >> 4)) 110 111 #define RX_FIFO_SIZE_SETTING(dev) \ 112 (sys_read32(SPI_CONFIG(dev)) & CFG_RX_FIFO_SIZE_MSK) 113 #define RX_FIFO_SIZE(dev) \ 114 (2 << (RX_FIFO_SIZE_SETTING(dev) >> 0)) 115 116 #define TX_NUM_STAT(dev) (sys_read32(SPI_STAT(dev)) & STAT_TX_NUM_MSK) 117 #define RX_NUM_STAT(dev) (sys_read32(SPI_STAT(dev)) & STAT_RX_NUM_MSK) 118 #define GET_TX_NUM(dev) (TX_NUM_STAT(dev) >> 16) 119 #define GET_RX_NUM(dev) (RX_NUM_STAT(dev) >> 8) 120
