1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_uart
8
9 #include <zephyr/sys/__assert.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/uart.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/pm/device.h>
16 #include <zephyr/pm/policy.h>
17 #include <soc.h>
18 #include "soc_miwu.h"
19 #include "soc_power.h"
20
21 #include <zephyr/logging/log.h>
22 #include <zephyr/irq.h>
23 LOG_MODULE_REGISTER(uart_npcx, CONFIG_UART_LOG_LEVEL);
24
25 /* Driver config */
26 struct uart_npcx_config {
27 struct uart_reg *inst;
28 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
29 uart_irq_config_func_t irq_config_func;
30 #endif
31 /* clock configuration */
32 struct npcx_clk_cfg clk_cfg;
33 /* int-mux configuration */
34 const struct npcx_wui uart_rx_wui;
35 /* pinmux configuration */
36 const struct pinctrl_dev_config *pcfg;
37 };
38
39 enum uart_pm_policy_state_flag {
40 UART_PM_POLICY_STATE_TX_FLAG,
41 UART_PM_POLICY_STATE_RX_FLAG,
42
43 UART_PM_POLICY_STATE_FLAG_COUNT,
44 };
45
46 /* Driver data */
47 struct uart_npcx_data {
48 /* Baud rate */
49 uint32_t baud_rate;
50 struct miwu_callback uart_rx_cb;
51 struct k_spinlock lock;
52 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
53 uart_irq_callback_user_data_t user_cb;
54 void *user_data;
55 #endif
56 #ifdef CONFIG_PM
57 ATOMIC_DEFINE(pm_policy_state_flag, UART_PM_POLICY_STATE_FLAG_COUNT);
58 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
59 struct k_work_delayable rx_refresh_timeout_work;
60 #endif
61 #endif
62 };
63
64 #ifdef CONFIG_PM
uart_npcx_pm_policy_state_lock_get(struct uart_npcx_data * data,enum uart_pm_policy_state_flag flag)65 static void uart_npcx_pm_policy_state_lock_get(struct uart_npcx_data *data,
66 enum uart_pm_policy_state_flag flag)
67 {
68 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
69 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
70 }
71 }
72
uart_npcx_pm_policy_state_lock_put(struct uart_npcx_data * data,enum uart_pm_policy_state_flag flag)73 static void uart_npcx_pm_policy_state_lock_put(struct uart_npcx_data *data,
74 enum uart_pm_policy_state_flag flag)
75 {
76 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
77 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
78 }
79 }
80 #endif
81
82 /* UART local functions */
uart_set_npcx_baud_rate(struct uart_reg * const inst,int baud_rate,int src_clk)83 static int uart_set_npcx_baud_rate(struct uart_reg *const inst, int baud_rate, int src_clk)
84 {
85 /* Fix baud rate to 115200 so far */
86 if (baud_rate == 115200) {
87 if (src_clk == 15000000) {
88 inst->UPSR = 0x38;
89 inst->UBAUD = 0x01;
90 } else if (src_clk == 20000000) {
91 inst->UPSR = 0x08;
92 inst->UBAUD = 0x0a;
93 } else {
94 return -EINVAL;
95 }
96 } else {
97 return -EINVAL;
98 }
99
100 return 0;
101 }
102
103 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_npcx_tx_fifo_ready(const struct device * dev)104 static int uart_npcx_tx_fifo_ready(const struct device *dev)
105 {
106 const struct uart_npcx_config *const config = dev->config;
107 struct uart_reg *const inst = config->inst;
108
109 /* True if the Tx FIFO is not completely full */
110 return !(GET_FIELD(inst->UFTSTS, NPCX_UFTSTS_TEMPTY_LVL) == 0);
111 }
112
uart_npcx_rx_fifo_available(const struct device * dev)113 static int uart_npcx_rx_fifo_available(const struct device *dev)
114 {
115 const struct uart_npcx_config *const config = dev->config;
116 struct uart_reg *const inst = config->inst;
117
118 /* True if at least one byte is in the Rx FIFO */
119 return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);
120 }
121
uart_npcx_dis_all_tx_interrupts(const struct device * dev)122 static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
123 {
124 const struct uart_npcx_config *const config = dev->config;
125 struct uart_reg *const inst = config->inst;
126
127 /* Disable all Tx interrupts */
128 inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
129 BIT(NPCX_UFTCTL_TEMPTY_EN) |
130 BIT(NPCX_UFTCTL_NXMIP_EN));
131 }
132
uart_npcx_clear_rx_fifo(const struct device * dev)133 static void uart_npcx_clear_rx_fifo(const struct device *dev)
134 {
135 const struct uart_npcx_config *const config = dev->config;
136 struct uart_reg *const inst = config->inst;
137 uint8_t scratch;
138
139 /* Read all dummy bytes out from Rx FIFO */
140 while (uart_npcx_rx_fifo_available(dev))
141 scratch = inst->URBUF;
142 }
143
uart_npcx_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)144 static int uart_npcx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
145 {
146 const struct uart_npcx_config *const config = dev->config;
147 struct uart_reg *const inst = config->inst;
148 struct uart_npcx_data *data = dev->data;
149 uint8_t tx_bytes = 0U;
150 k_spinlock_key_t key = k_spin_lock(&data->lock);
151
152 /* If Tx FIFO is still ready to send */
153 while ((size - tx_bytes > 0) && uart_npcx_tx_fifo_ready(dev)) {
154 /* Put a character into Tx FIFO */
155 inst->UTBUF = tx_data[tx_bytes++];
156 }
157 #ifdef CONFIG_PM
158 uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_TX_FLAG);
159 /* Enable NXMIP interrupt in case ec enters deep sleep early */
160 inst->UFTCTL |= BIT(NPCX_UFTCTL_NXMIP_EN);
161 #endif /* CONFIG_PM */
162 k_spin_unlock(&data->lock, key);
163
164 return tx_bytes;
165 }
166
uart_npcx_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)167 static int uart_npcx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
168 {
169 const struct uart_npcx_config *const config = dev->config;
170 struct uart_reg *const inst = config->inst;
171 unsigned int rx_bytes = 0U;
172
173 /* If least one byte is in the Rx FIFO */
174 while ((size - rx_bytes > 0) && uart_npcx_rx_fifo_available(dev)) {
175 /* Receive one byte from Rx FIFO */
176 rx_data[rx_bytes++] = inst->URBUF;
177 }
178
179 return rx_bytes;
180 }
181
uart_npcx_irq_tx_enable(const struct device * dev)182 static void uart_npcx_irq_tx_enable(const struct device *dev)
183 {
184 const struct uart_npcx_config *const config = dev->config;
185 struct uart_reg *const inst = config->inst;
186 struct uart_npcx_data *data = dev->data;
187 k_spinlock_key_t key = k_spin_lock(&data->lock);
188
189 inst->UFTCTL |= BIT(NPCX_UFTCTL_TEMPTY_EN);
190 k_spin_unlock(&data->lock, key);
191 }
192
uart_npcx_irq_tx_disable(const struct device * dev)193 static void uart_npcx_irq_tx_disable(const struct device *dev)
194 {
195 const struct uart_npcx_config *const config = dev->config;
196 struct uart_reg *const inst = config->inst;
197 struct uart_npcx_data *data = dev->data;
198 k_spinlock_key_t key = k_spin_lock(&data->lock);
199
200 inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_EN));
201 k_spin_unlock(&data->lock, key);
202 }
203
uart_npcx_irq_tx_is_enabled(const struct device * dev)204 static bool uart_npcx_irq_tx_is_enabled(const struct device *dev)
205 {
206 const struct uart_npcx_config *const config = dev->config;
207 struct uart_reg *const inst = config->inst;
208
209 return IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_TEMPTY_EN);
210 }
211
uart_npcx_irq_tx_ready(const struct device * dev)212 static int uart_npcx_irq_tx_ready(const struct device *dev)
213 {
214 return uart_npcx_tx_fifo_ready(dev) && uart_npcx_irq_tx_is_enabled(dev);
215 }
216
uart_npcx_irq_tx_complete(const struct device * dev)217 static int uart_npcx_irq_tx_complete(const struct device *dev)
218 {
219 const struct uart_npcx_config *const config = dev->config;
220 struct uart_reg *const inst = config->inst;
221
222 /* Tx FIFO is empty or last byte is sending */
223 return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);
224 }
225
uart_npcx_irq_rx_enable(const struct device * dev)226 static void uart_npcx_irq_rx_enable(const struct device *dev)
227 {
228 const struct uart_npcx_config *const config = dev->config;
229 struct uart_reg *const inst = config->inst;
230
231 inst->UFRCTL |= BIT(NPCX_UFRCTL_RNEMPTY_EN);
232 }
233
uart_npcx_irq_rx_disable(const struct device * dev)234 static void uart_npcx_irq_rx_disable(const struct device *dev)
235 {
236 const struct uart_npcx_config *const config = dev->config;
237 struct uart_reg *const inst = config->inst;
238
239 inst->UFRCTL &= ~(BIT(NPCX_UFRCTL_RNEMPTY_EN));
240 }
241
uart_npcx_irq_rx_is_enabled(const struct device * dev)242 static bool uart_npcx_irq_rx_is_enabled(const struct device *dev)
243 {
244 const struct uart_npcx_config *const config = dev->config;
245 struct uart_reg *const inst = config->inst;
246
247 return IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN);
248 }
249
uart_npcx_irq_rx_ready(const struct device * dev)250 static int uart_npcx_irq_rx_ready(const struct device *dev)
251 {
252 return uart_npcx_rx_fifo_available(dev);
253 }
254
uart_npcx_irq_err_enable(const struct device * dev)255 static void uart_npcx_irq_err_enable(const struct device *dev)
256 {
257 const struct uart_npcx_config *const config = dev->config;
258 struct uart_reg *const inst = config->inst;
259
260 inst->UICTRL |= BIT(NPCX_UICTRL_EEI);
261 }
262
uart_npcx_irq_err_disable(const struct device * dev)263 static void uart_npcx_irq_err_disable(const struct device *dev)
264 {
265 const struct uart_npcx_config *const config = dev->config;
266 struct uart_reg *const inst = config->inst;
267
268 inst->UICTRL &= ~(BIT(NPCX_UICTRL_EEI));
269 }
270
uart_npcx_irq_is_pending(const struct device * dev)271 static int uart_npcx_irq_is_pending(const struct device *dev)
272 {
273 return uart_npcx_irq_tx_ready(dev) ||
274 (uart_npcx_irq_rx_ready(dev) && uart_npcx_irq_rx_is_enabled(dev));
275 }
276
uart_npcx_irq_update(const struct device * dev)277 static int uart_npcx_irq_update(const struct device *dev)
278 {
279 ARG_UNUSED(dev);
280
281 return 1;
282 }
283
uart_npcx_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)284 static void uart_npcx_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
285 void *cb_data)
286 {
287 struct uart_npcx_data *data = dev->data;
288
289 data->user_cb = cb;
290 data->user_data = cb_data;
291 }
292
uart_npcx_isr(const struct device * dev)293 static void uart_npcx_isr(const struct device *dev)
294 {
295 struct uart_npcx_data *data = dev->data;
296
297 /*
298 * Set pm constraint to prevent the system enter suspend state within
299 * the CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT period.
300 */
301 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
302 if (uart_npcx_irq_rx_ready(dev)) {
303 k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
304
305 uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_RX_FLAG);
306 k_work_reschedule(&data->rx_refresh_timeout_work, delay);
307 }
308 #endif
309
310 if (data->user_cb) {
311 data->user_cb(dev, data->user_data);
312 }
313 #ifdef CONFIG_PM
314 const struct uart_npcx_config *const config = dev->config;
315 struct uart_reg *const inst = config->inst;
316
317 if (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_NXMIP_EN) &&
318 IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP)) {
319 k_spinlock_key_t key = k_spin_lock(&data->lock);
320
321 /* Disable NXMIP interrupt */
322 inst->UFTCTL &= ~BIT(NPCX_UFTCTL_NXMIP_EN);
323 k_spin_unlock(&data->lock, key);
324 uart_npcx_pm_policy_state_lock_put(data, UART_PM_POLICY_STATE_TX_FLAG);
325 }
326 #endif /* CONFIG_PM */
327 }
328
329 /*
330 * Poll-in implementation for interrupt driven config, forward call to
331 * uart_npcx_fifo_read().
332 */
uart_npcx_poll_in(const struct device * dev,unsigned char * c)333 static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
334 {
335 return uart_npcx_fifo_read(dev, c, 1) ? 0 : -1;
336 }
337
338 /*
339 * Poll-out implementation for interrupt driven config, forward call to
340 * uart_npcx_fifo_fill().
341 */
uart_npcx_poll_out(const struct device * dev,unsigned char c)342 static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
343 {
344 while (!uart_npcx_fifo_fill(dev, &c, 1))
345 continue;
346 }
347
348 #else /* !CONFIG_UART_INTERRUPT_DRIVEN */
349
350 /*
351 * Poll-in implementation for byte mode config, read byte from URBUF if
352 * available.
353 */
uart_npcx_poll_in(const struct device * dev,unsigned char * c)354 static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
355 {
356 const struct uart_npcx_config *const config = dev->config;
357 struct uart_reg *const inst = config->inst;
358
359 /* Rx single byte buffer is not full */
360 if (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_RBF))
361 return -1;
362
363 *c = inst->URBUF;
364 return 0;
365 }
366
367 /*
368 * Poll-out implementation for byte mode config, write byte to UTBUF if empty.
369 */
uart_npcx_poll_out(const struct device * dev,unsigned char c)370 static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
371 {
372 const struct uart_npcx_config *const config = dev->config;
373 struct uart_reg *const inst = config->inst;
374
375 /* Wait while Tx single byte buffer is ready to send */
376 while (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_TBE))
377 continue;
378
379 inst->UTBUF = c;
380 }
381 #endif /* !CONFIG_UART_INTERRUPT_DRIVEN */
382
383 /* UART api functions */
uart_npcx_err_check(const struct device * dev)384 static int uart_npcx_err_check(const struct device *dev)
385 {
386 const struct uart_npcx_config *const config = dev->config;
387 struct uart_reg *const inst = config->inst;
388 uint32_t err = 0U;
389 uint8_t stat = inst->USTAT;
390
391 if (IS_BIT_SET(stat, NPCX_USTAT_DOE))
392 err |= UART_ERROR_OVERRUN;
393
394 if (IS_BIT_SET(stat, NPCX_USTAT_PE))
395 err |= UART_ERROR_PARITY;
396
397 if (IS_BIT_SET(stat, NPCX_USTAT_FE))
398 err |= UART_ERROR_FRAMING;
399
400 return err;
401 }
402
uart_npcx_rx_wk_isr(const struct device * dev,struct npcx_wui * wui)403 static __unused void uart_npcx_rx_wk_isr(const struct device *dev, struct npcx_wui *wui)
404 {
405 /*
406 * Set pm constraint to prevent the system enter suspend state within
407 * the CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT period.
408 */
409 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
410 struct uart_npcx_data *data = dev->data;
411 k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
412
413 uart_npcx_pm_policy_state_lock_get(data, UART_PM_POLICY_STATE_RX_FLAG);
414 k_work_reschedule(&data->rx_refresh_timeout_work, delay);
415 #endif
416
417 /*
418 * Disable MIWU CR_SIN interrupt to avoid the other redundant interrupts
419 * after ec wakes up.
420 */
421 npcx_uart_disable_access_interrupt();
422 }
423
424 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
uart_npcx_rx_refresh_timeout(struct k_work * work)425 static void uart_npcx_rx_refresh_timeout(struct k_work *work)
426 {
427 struct k_work_delayable *dwork = k_work_delayable_from_work(work);
428 struct uart_npcx_data *data =
429 CONTAINER_OF(dwork, struct uart_npcx_data, rx_refresh_timeout_work);
430
431 uart_npcx_pm_policy_state_lock_put(data, UART_PM_POLICY_STATE_RX_FLAG);
432 }
433 #endif
434
435 /* UART driver registration */
436 static const struct uart_driver_api uart_npcx_driver_api = {
437 .poll_in = uart_npcx_poll_in,
438 .poll_out = uart_npcx_poll_out,
439 .err_check = uart_npcx_err_check,
440 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
441 .fifo_fill = uart_npcx_fifo_fill,
442 .fifo_read = uart_npcx_fifo_read,
443 .irq_tx_enable = uart_npcx_irq_tx_enable,
444 .irq_tx_disable = uart_npcx_irq_tx_disable,
445 .irq_tx_ready = uart_npcx_irq_tx_ready,
446 .irq_tx_complete = uart_npcx_irq_tx_complete,
447 .irq_rx_enable = uart_npcx_irq_rx_enable,
448 .irq_rx_disable = uart_npcx_irq_rx_disable,
449 .irq_rx_ready = uart_npcx_irq_rx_ready,
450 .irq_err_enable = uart_npcx_irq_err_enable,
451 .irq_err_disable = uart_npcx_irq_err_disable,
452 .irq_is_pending = uart_npcx_irq_is_pending,
453 .irq_update = uart_npcx_irq_update,
454 .irq_callback_set = uart_npcx_irq_callback_set,
455 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
456 };
457
uart_npcx_init(const struct device * dev)458 static int uart_npcx_init(const struct device *dev)
459 {
460 const struct uart_npcx_config *const config = dev->config;
461 struct uart_npcx_data *const data = dev->data;
462 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
463 struct uart_reg *const inst = config->inst;
464 uint32_t uart_rate;
465 int ret;
466
467 if (!device_is_ready(clk_dev)) {
468 LOG_ERR("clock control device not ready");
469 return -ENODEV;
470 }
471
472 /* Turn on device clock first and get source clock freq. */
473 ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
474 if (ret < 0) {
475 LOG_ERR("Turn on UART clock fail %d", ret);
476 return ret;
477 }
478
479 /*
480 * If apb2's clock is not 15MHz, we need to find the other optimized
481 * values of UPSR and UBAUD for baud rate 115200.
482 */
483 ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg,
484 &uart_rate);
485 if (ret < 0) {
486 LOG_ERR("Get UART clock rate error %d", ret);
487 return ret;
488 }
489
490 /* Configure baud rate */
491 ret = uart_set_npcx_baud_rate(inst, data->baud_rate, uart_rate);
492 if (ret < 0) {
493 LOG_ERR("Set baud rate %d with unsupported apb clock %d failed", data->baud_rate,
494 uart_rate);
495 return ret;
496 }
497
498 /*
499 * 8-N-1, FIFO enabled. Must be done after setting
500 * the divisor for the new divisor to take effect.
501 */
502 inst->UFRS = 0x00;
503
504 /* Initialize UART FIFO if mode is interrupt driven */
505 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
506 /* Enable the UART FIFO mode */
507 inst->UMDSL |= BIT(NPCX_UMDSL_FIFO_MD);
508
509 /* Disable all UART tx FIFO interrupts */
510 uart_npcx_dis_all_tx_interrupts(dev);
511
512 /* Clear UART rx FIFO */
513 uart_npcx_clear_rx_fifo(dev);
514
515 /* Configure UART interrupts */
516 config->irq_config_func(dev);
517 #endif
518
519 if (IS_ENABLED(CONFIG_PM)) {
520 /* Initialize a miwu device input and its callback function */
521 npcx_miwu_init_dev_callback(&data->uart_rx_cb, &config->uart_rx_wui,
522 uart_npcx_rx_wk_isr, dev);
523 npcx_miwu_manage_callback(&data->uart_rx_cb, true);
524 /*
525 * Configure the UART wake-up event triggered from a falling
526 * edge on CR_SIN pin. No need for callback function.
527 */
528 npcx_miwu_interrupt_configure(&config->uart_rx_wui, NPCX_MIWU_MODE_EDGE,
529 NPCX_MIWU_TRIG_LOW);
530
531 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
532 k_work_init_delayable(&data->rx_refresh_timeout_work, uart_npcx_rx_refresh_timeout);
533 #endif
534 }
535
536 /* Configure pin-mux for uart device */
537 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
538 if (ret < 0) {
539 LOG_ERR("UART pinctrl setup failed (%d)", ret);
540 return ret;
541 }
542
543 return 0;
544 }
545
546 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
547 #define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst) \
548 static void uart_npcx_irq_config_##inst(const struct device *dev)
549 #define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst) .irq_config_func = uart_npcx_irq_config_##inst,
550 #define NPCX_UART_IRQ_CONFIG_FUNC(inst) \
551 static void uart_npcx_irq_config_##inst(const struct device *dev) \
552 { \
553 IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), uart_npcx_isr, \
554 DEVICE_DT_INST_GET(inst), 0); \
555 irq_enable(DT_INST_IRQN(inst)); \
556 }
557 #else
558 #define NPCX_UART_IRQ_CONFIG_FUNC_DECL(inst)
559 #define NPCX_UART_IRQ_CONFIG_FUNC_INIT(inst)
560 #define NPCX_UART_IRQ_CONFIG_FUNC(inst)
561 #endif
562
563 #define NPCX_UART_INIT(i) \
564 NPCX_UART_IRQ_CONFIG_FUNC_DECL(i); \
565 \
566 PINCTRL_DT_INST_DEFINE(i); \
567 \
568 static const struct uart_npcx_config uart_npcx_cfg_##i = { \
569 .inst = (struct uart_reg *)DT_INST_REG_ADDR(i), \
570 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(i), \
571 .uart_rx_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, uart_rx), \
572 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
573 NPCX_UART_IRQ_CONFIG_FUNC_INIT(i) \
574 }; \
575 \
576 static struct uart_npcx_data uart_npcx_data_##i = { .baud_rate = DT_INST_PROP( \
577 i, current_speed) }; \
578 \
579 DEVICE_DT_INST_DEFINE(i, &uart_npcx_init, NULL, &uart_npcx_data_##i, \
580 &uart_npcx_cfg_##i, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
581 &uart_npcx_driver_api); \
582 \
583 NPCX_UART_IRQ_CONFIG_FUNC(i)
584
DT_INST_FOREACH_STATUS_OKAY(NPCX_UART_INIT)585 DT_INST_FOREACH_STATUS_OKAY(NPCX_UART_INIT)
586
587 #define ENABLE_MIWU_CRIN_IRQ(i) \
588 npcx_miwu_irq_get_and_clear_pending(&uart_npcx_cfg_##i.uart_rx_wui); \
589 npcx_miwu_irq_enable(&uart_npcx_cfg_##i.uart_rx_wui);
590
591 #define DISABLE_MIWU_CRIN_IRQ(i) npcx_miwu_irq_disable(&uart_npcx_cfg_##i.uart_rx_wui);
592
593 void npcx_uart_enable_access_interrupt(void)
594 {
595 DT_INST_FOREACH_STATUS_OKAY(ENABLE_MIWU_CRIN_IRQ)
596 }
597
npcx_uart_disable_access_interrupt(void)598 void npcx_uart_disable_access_interrupt(void)
599 {
600 DT_INST_FOREACH_STATUS_OKAY(DISABLE_MIWU_CRIN_IRQ)
601 }
602
