1# nrfx UART configuration
2
3# Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6menuconfig UART_NRFX
7	bool "nRF UART nrfx drivers"
8	default y
9	select SERIAL_HAS_DRIVER
10	select SERIAL_SUPPORT_INTERRUPT
11	select SERIAL_SUPPORT_ASYNC
12	select PINCTRL
13	depends on DT_HAS_NORDIC_NRF_UART_ENABLED || DT_HAS_NORDIC_NRF_UARTE_ENABLED
14	help
15	  Enable support for nrfx UART drivers for nRF MCU series.
16	  Peripherals with the same instance ID cannot be used together,
17	  e.g. UART_0 and UARTE_0.
18
19if UART_NRFX
20
21config UART_NRFX_UART
22	def_bool y
23	depends on DT_HAS_NORDIC_NRF_UART_ENABLED
24
25config UART_NRFX_UARTE
26	def_bool y
27	depends on DT_HAS_NORDIC_NRF_UARTE_ENABLED
28
29config UART_ASYNC_TX_CACHE_SIZE
30	int "TX cache buffer size"
31	depends on UART_ASYNC_API
32	depends on UART_NRFX_UARTE
33	default 8
34	help
35	  For UARTE, TX cache buffer is used when provided TX buffer is not located
36	  in RAM, because EasyDMA in UARTE peripherals can only transfer data
37	  from RAM.
38
39# ----------------- port 0 -----------------
40if HAS_HW_NRF_UART0 || HAS_HW_NRF_UARTE0
41
42config UART_0_ENHANCED_POLL_OUT
43	bool "Efficient poll out on port 0"
44	default y
45	depends on HAS_HW_NRF_UARTE0
46	help
47	  When enabled, polling out does not trigger interrupt which stops TX.
48	  Feature uses a PPI channel.
49
50config UART_0_INTERRUPT_DRIVEN
51	bool "Interrupt support on port 0"
52	depends on UART_INTERRUPT_DRIVEN
53	default y
54	help
55	  This option enables UART interrupt support on port 0.
56
57config UART_0_ASYNC
58	bool "Asynchronous API support on port 0"
59	depends on UART_ASYNC_API && !UART_0_INTERRUPT_DRIVEN
60	default y
61	help
62	  This option enables UART Asynchronous API support on port 0.
63
64config UART_0_NRF_PARITY_BIT
65	bool "Parity bit"
66	help
67	  Enable parity bit.
68
69config UART_0_NRF_TX_BUFFER_SIZE
70	int "Size of RAM buffer"
71	depends on HAS_HW_NRF_UARTE0
72	range 1 65535
73	default 32
74	help
75	  Size of the transmit buffer for API function: fifo_fill.
76	  This value is limited by range of TXD.MAXCNT register for
77	  particular SoC.
78
79config UART_0_NRF_HW_ASYNC
80	bool "Use hardware RX byte counting"
81	depends on HAS_HW_NRF_UARTE0
82	depends on UART_ASYNC_API
83	help
84	  If default driver uses interrupts to count incoming bytes, it is possible
85	  that with higher speeds and/or high cpu load some data can be lost.
86	  It is recommended to use hardware byte counting in such scenarios.
87	  Hardware RX byte counting requires timer instance and one PPI channel
88
89config UART_0_NRF_ASYNC_LOW_POWER
90	bool "Low power mode"
91	depends on HAS_HW_NRF_UARTE0
92	depends on UART_ASYNC_API
93	help
94	  When enabled, UARTE is enabled before each TX or RX usage and disabled
95	  when not used. Disabling UARTE while in idle allows to achieve lowest
96	  power consumption. It is only feasible if receiver is not always on.
97
98config UART_0_NRF_HW_ASYNC_TIMER
99	int "Timer instance"
100	depends on UART_0_NRF_HW_ASYNC
101
102config UART_0_GPIO_MANAGEMENT
103	bool "GPIO management on port 0"
104	depends on PM_DEVICE
105	default y
106	help
107	  If enabled, the driver will configure the GPIOs used by the uart to
108	  their default configuration when device is powered down. The GPIOs
109	  will be configured back to correct state when UART is powered up.
110
111endif # HAS_HW_NRF_UART0 || HAS_HW_NRF_UARTE0
112
113# ----------------- port 1 -----------------
114if HAS_HW_NRF_UARTE1
115
116config UART_1_INTERRUPT_DRIVEN
117	bool "Interrupt support on port 1"
118	depends on UART_INTERRUPT_DRIVEN
119	default y
120	help
121	  This option enables UART interrupt support on port 1.
122
123config UART_1_ASYNC
124	bool "Asynchronous API support on port 1"
125	depends on UART_ASYNC_API && !UART_1_INTERRUPT_DRIVEN
126	default y
127	help
128	  This option enables UART Asynchronous API support on port 1.
129
130config UART_1_ENHANCED_POLL_OUT
131	bool "Efficient poll out on port 1"
132	default y
133	help
134	  When enabled, polling out does not trigger interrupt which stops TX.
135	  Feature uses a PPI channel.
136
137config UART_1_NRF_PARITY_BIT
138	bool "Parity bit"
139	help
140	  Enable parity bit.
141
142config UART_1_NRF_TX_BUFFER_SIZE
143	int "Size of RAM buffer"
144	depends on UART_INTERRUPT_DRIVEN
145	range 1 65535
146	default 32
147	help
148	  Size of the transmit buffer for API function: fifo_fill.
149	  This value is limited by range of TXD.MAXCNT register for
150	  particular SoC.
151
152config UART_1_NRF_HW_ASYNC
153	bool "Use hardware RX byte counting"
154	depends on UART_1_ASYNC
155	help
156	  If default driver uses interrupts to count incoming bytes, it is possible
157	  that with higher speeds and/or high cpu load some data can be lost.
158	  It is recommended to use hardware byte counting in such scenarios.
159	  Hardware RX byte counting requires timer instance and one PPI channel
160
161config UART_1_NRF_ASYNC_LOW_POWER
162	bool "Low power mode"
163	depends on UART_ASYNC_API
164	help
165	  When enabled, UARTE is enabled before each TX or RX usage and disabled
166	  when not used. Disabling UARTE while in idle allows to achieve lowest
167	  power consumption. It is only feasible if receiver is not always on.
168
169config UART_1_NRF_HW_ASYNC_TIMER
170	int "Timer instance"
171	depends on UART_1_NRF_HW_ASYNC
172
173config UART_1_GPIO_MANAGEMENT
174	bool "GPIO management on port 1"
175	depends on PM_DEVICE
176	default y
177	help
178	  If enabled, the driver will configure the GPIOs used by the uart to
179	  their default configuration when device is powered down. The GPIOs
180	  will be configured back to correct state when UART is powered up.
181
182endif # HAS_HW_NRF_UARTE1
183
184# ----------------- port 2 -----------------
185if HAS_HW_NRF_UARTE2
186
187config UART_2_INTERRUPT_DRIVEN
188	bool "Interrupt support on port 2"
189	depends on UART_INTERRUPT_DRIVEN
190	default y
191	help
192	  This option enables UART interrupt support on port 2.
193
194config UART_2_ASYNC
195	bool "Asynchronous API support on port 2"
196	depends on UART_ASYNC_API && !UART_2_INTERRUPT_DRIVEN
197	default y
198	help
199	  This option enables UART Asynchronous API support on port 2.
200
201config UART_2_ENHANCED_POLL_OUT
202	bool "Efficient poll out on port 2"
203	default y
204	help
205	  When enabled, polling out does not trigger interrupt which stops TX.
206	  Feature uses a PPI channel.
207
208config UART_2_NRF_PARITY_BIT
209	bool "Parity bit"
210	help
211	  Enable parity bit.
212
213config UART_2_NRF_TX_BUFFER_SIZE
214	int "Size of RAM buffer"
215	range 1 65535
216	default 32
217	help
218	  Size of the transmit buffer for API function: fifo_fill.
219	  This value is limited by range of TXD.MAXCNT register for
220	  particular SoC.
221
222config UART_2_NRF_HW_ASYNC
223	bool "Use hardware RX byte counting"
224	depends on UART_2_ASYNC
225	help
226	  If default driver uses interrupts to count incoming bytes, it is possible
227	  that with higher speeds and/or high cpu load some data can be lost.
228	  It is recommended to use hardware byte counting in such scenarios.
229	  Hardware RX byte counting requires timer instance and one PPI channel
230
231config UART_2_NRF_ASYNC_LOW_POWER
232	bool "Low power mode"
233	depends on UART_ASYNC_API
234	help
235	  When enabled, UARTE is enabled before each TX or RX usage and disabled
236	  when not used. Disabling UARTE while in idle allows to achieve lowest
237	  power consumption. It is only feasible if receiver is not always on.
238
239config UART_2_NRF_HW_ASYNC_TIMER
240	int "Timer instance"
241	depends on UART_2_NRF_HW_ASYNC
242
243config UART_2_GPIO_MANAGEMENT
244	bool "GPIO management on port 2"
245	depends on PM_DEVICE
246	default y
247	help
248	  If enabled, the driver will configure the GPIOs used by the uart to
249	  their default configuration when device is powered down. The GPIOs
250	  will be configured back to correct state when UART is powered up.
251
252endif # HAS_HW_NRF_UARTE2
253
254# ----------------- port 3 -----------------
255if HAS_HW_NRF_UARTE3
256
257config UART_3_INTERRUPT_DRIVEN
258	bool "Interrupt support on port 3"
259	depends on UART_INTERRUPT_DRIVEN
260	default y
261	help
262	  This option enables UART interrupt support on port 3.
263
264config UART_3_ASYNC
265	bool "Asynchronous API support on port 3"
266	depends on UART_ASYNC_API && !UART_3_INTERRUPT_DRIVEN
267	default y
268	help
269	  This option enables UART Asynchronous API support on port 3.
270
271config UART_3_ENHANCED_POLL_OUT
272	bool "Efficient poll out on port 3"
273	default y
274	help
275	  When enabled, polling out does not trigger interrupt which stops TX.
276	  Feature uses a PPI channel.
277
278config UART_3_NRF_PARITY_BIT
279	bool "Parity bit"
280	help
281	  Enable parity bit.
282
283config UART_3_NRF_TX_BUFFER_SIZE
284	int "Size of RAM buffer"
285	range 1 65535
286	default 32
287	help
288	  Size of the transmit buffer for API function: fifo_fill.
289	  This value is limited by range of TXD.MAXCNT register for
290	  particular SoC.
291
292config UART_3_NRF_HW_ASYNC
293	bool "Use hardware RX byte counting"
294	depends on UART_3_ASYNC
295	help
296	  If default driver uses interrupts to count incoming bytes, it is possible
297	  that with higher speeds and/or high cpu load some data can be lost.
298	  It is recommended to use hardware byte counting in such scenarios.
299	  Hardware RX byte counting requires timer instance and one PPI channel
300
301config UART_3_NRF_ASYNC_LOW_POWER
302	bool "Low power mode"
303	depends on UART_ASYNC_API
304	help
305	  When enabled, UARTE is enabled before each TX or RX usage and disabled
306	  when not used. Disabling UARTE while in idle allows to achieve lowest
307	  power consumption. It is only feasible if receiver is not always on.
308
309config UART_3_NRF_HW_ASYNC_TIMER
310	int "Timer instance"
311	depends on UART_3_NRF_HW_ASYNC
312
313config UART_3_GPIO_MANAGEMENT
314	bool "GPIO management on port 3"
315	depends on PM_DEVICE
316	default y
317	help
318	  If enabled, the driver will configure the GPIOs used by the uart to
319	  their default configuration when device is powered down. The GPIOs
320	  will be configured back to correct state when UART is powered up.
321
322endif # HAS_HW_NRF_UARTE3
323
324
325config NRFX_TIMER0
326	default y
327	depends on UART_0_NRF_HW_ASYNC_TIMER = 0 \
328		|| UART_1_NRF_HW_ASYNC_TIMER = 0 \
329		|| UART_2_NRF_HW_ASYNC_TIMER = 0 \
330		|| UART_3_NRF_HW_ASYNC_TIMER = 0
331
332config NRFX_TIMER1
333	default y
334	depends on UART_0_NRF_HW_ASYNC_TIMER = 1 \
335		|| UART_1_NRF_HW_ASYNC_TIMER = 1 \
336		|| UART_2_NRF_HW_ASYNC_TIMER = 1 \
337		|| UART_3_NRF_HW_ASYNC_TIMER = 1
338
339config NRFX_TIMER2
340	default y
341	depends on UART_0_NRF_HW_ASYNC_TIMER = 2 \
342		|| UART_1_NRF_HW_ASYNC_TIMER = 2 \
343		|| UART_2_NRF_HW_ASYNC_TIMER = 2 \
344		|| UART_3_NRF_HW_ASYNC_TIMER = 2
345
346config NRFX_TIMER3
347	default y
348	depends on UART_0_NRF_HW_ASYNC_TIMER = 3 \
349		|| UART_1_NRF_HW_ASYNC_TIMER = 3 \
350		|| UART_2_NRF_HW_ASYNC_TIMER = 3 \
351		|| UART_3_NRF_HW_ASYNC_TIMER = 3
352
353config NRFX_TIMER4
354	default y
355	depends on UART_0_NRF_HW_ASYNC_TIMER = 4 \
356		|| UART_1_NRF_HW_ASYNC_TIMER = 4 \
357		|| UART_2_NRF_HW_ASYNC_TIMER = 4 \
358		|| UART_3_NRF_HW_ASYNC_TIMER = 4
359
360
361config UARTE_NRF_HW_ASYNC
362	def_bool y
363	depends on UART_0_NRF_HW_ASYNC \
364		|| UART_1_NRF_HW_ASYNC \
365		|| UART_2_NRF_HW_ASYNC \
366		|| UART_3_NRF_HW_ASYNC
367	select NRFX_PPI if HAS_HW_NRF_PPI
368	select NRFX_DPPI if HAS_HW_NRF_DPPIC
369
370config UART_ENHANCED_POLL_OUT
371	def_bool y
372	depends on UART_0_ENHANCED_POLL_OUT \
373		|| UART_1_ENHANCED_POLL_OUT \
374		|| UART_2_ENHANCED_POLL_OUT \
375		|| UART_3_ENHANCED_POLL_OUT
376	select NRFX_PPI if HAS_HW_NRF_PPI
377	select NRFX_DPPI if HAS_HW_NRF_DPPIC
378
379endif # UART_NRFX
380