1# Copyright (c) 2023 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4config UART_ALTERA
5	bool "ALTERA UART driver"
6	depends on DT_HAS_ALTR_UART_ENABLED
7	select SERIAL_HAS_DRIVER
8	select SERIAL_SUPPORT_INTERRUPT
9	help
10	  Enable the Altera UART driver, that can be built into Intel NiosV CPU designs.
11
12config UART_ALTERA_EOP
13	bool "ALTERA UART end of packet feature"
14	depends on UART_ALTERA && UART_DRV_CMD && UART_INTERRUPT_DRIVEN
15	help
16	  Use driver command CMD_ENABLE_EOP and CMD_DISABLE_EOP to use the feature.
17
18config UART_ALTERA_LINE_CTRL_WORKAROUND
19	bool "ALTERA UART flow control workaround"
20	depends on UART_ALTERA && UART_LINE_CTRL
21	help
22	  Before enabling this, please try to optimise the ISR to fetch the receive data faster.
23	  Enabling this will cause the transmitter to wait for rising edge of CTS before sending.
24	  The receiver will deassert RTS as soon as a byte is received and reassert after the byte is fetched.
25