1 /*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2021 Linaro Limited
4 * Copyright (c) 2021 Nordic Semiconductor ASA
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #include <zephyr/init.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <gpio/gpio_stm32.h>
13
14 #include <stm32_ll_bus.h>
15 #include <stm32_ll_gpio.h>
16 #include <stm32_ll_system.h>
17
18 /** Helper to extract IO port number from STM32PIN() encoded value */
19 #define STM32_PORT(__pin) \
20 ((__pin) >> 4)
21
22 /** Helper to extract IO pin number from STM32PIN() encoded value */
23 #define STM32_PIN(__pin) \
24 ((__pin) & 0xf)
25
26 /** Helper to extract IO port number from STM32_PINMUX() encoded value */
27 #define STM32_DT_PINMUX_PORT(__pin) \
28 (((__pin) >> STM32_PORT_SHIFT) & STM32_PORT_MASK)
29
30 /** Helper to extract IO pin number from STM32_PINMUX() encoded value */
31 #define STM32_DT_PINMUX_LINE(__pin) \
32 (((__pin) >> STM32_LINE_SHIFT) & STM32_LINE_MASK)
33
34 /** Helper to extract IO pin func from STM32_PINMUX() encoded value */
35 #define STM32_DT_PINMUX_FUNC(__pin) \
36 (((__pin) >> STM32_MODE_SHIFT) & STM32_MODE_MASK)
37
38 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
39 /** Helper to extract IO pin remap from STM32_PINMUX() encoded value */
40 #define STM32_DT_PINMUX_REMAP(__pin) \
41 (((__pin) >> STM32_REMAP_SHIFT) & STM32_REMAP_MASK)
42 #endif
43
44 /**
45 * @brief Array containing pointers to each GPIO port.
46 *
47 * Entries will be NULL if the GPIO port is not enabled.
48 */
49 static const struct device *const gpio_ports[] = {
50 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioa)),
51 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiob)),
52 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioc)),
53 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiod)),
54 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioe)),
55 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiof)),
56 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiog)),
57 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioh)),
58 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioi)),
59 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioj)),
60 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiok)),
61 };
62
63 /** Number of GPIO ports. */
64 static const size_t gpio_ports_cnt = ARRAY_SIZE(gpio_ports);
65
66 #if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11)
67 #define REMAP_PA11 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11)
68 #endif
69 #if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa12)
70 #define REMAP_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa12)
71 #endif
72 #if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
73 #define REMAP_PA11_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
74 #endif
75
76 #if REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12
77
stm32_pinmux_init_remap(void)78 int stm32_pinmux_init_remap(void)
79 {
80
81 #if REMAP_PA11 || REMAP_PA12
82
83 #if !defined(CONFIG_SOC_SERIES_STM32G0X)
84 #error "Pin remap property available only on STM32G0 SoC series"
85 #endif
86
87 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
88 #if REMAP_PA11
89 LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
90 #endif
91 #if REMAP_PA12
92 LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
93 #endif
94
95 #elif REMAP_PA11_PA12
96
97 #if !defined(SYSCFG_CFGR1_PA11_PA12_RMP)
98 #error "Pin remap property available only on STM32F070x SoC series"
99 #endif
100
101 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
102 LL_SYSCFG_EnablePinRemap();
103
104 #endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
105
106 return 0;
107 }
108
109 SYS_INIT(stm32_pinmux_init_remap, PRE_KERNEL_1,
110 CONFIG_PINCTRL_STM32_REMAP_INIT_PRIORITY);
111
112 #endif /* REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12 */
113
114 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
115
116 /* ignore swj-cfg reset state (default value) */
117 #if ((DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg)) && \
118 (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) != 0))
119
stm32f1_swj_cfg_init(void)120 static int stm32f1_swj_cfg_init(void)
121 {
122
123 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
124
125 /* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */
126 /* only one of the 3 bits can be set */
127 #if (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 1)
128 /* 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST */
129 /* releases: PB4 */
130 LL_GPIO_AF_Remap_SWJ_NONJTRST();
131 #elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 2)
132 /* 010: JTAG-DP Disabled and SW-DP Enabled */
133 /* releases: PB4 PB3 PA15 */
134 LL_GPIO_AF_Remap_SWJ_NOJTAG();
135 #elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 3)
136 /* 100: JTAG-DP Disabled and SW-DP Disabled */
137 /* releases: PB4 PB3 PA13 PA14 PA15 */
138 LL_GPIO_AF_DisableRemap_SWJ();
139 #endif
140
141 return 0;
142 }
143
144 SYS_INIT(stm32f1_swj_cfg_init, PRE_KERNEL_1, 0);
145
146 #endif /* DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg) */
147
148 /**
149 * @brief Helper function to check and apply provided pinctrl remap
150 * configuration.
151 *
152 * Check operation verifies that pin remapping configuration is the same on all
153 * pins. If configuration is valid AFIO clock is enabled and remap is applied
154 *
155 * @param pins List of pins to be configured.
156 * @param pin_cnt Number of pins.
157 *
158 * @retval 0 If successful
159 * @retval -EINVAL If pins have an incompatible set of remaps.
160 */
stm32_pins_remap(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt)161 static int stm32_pins_remap(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt)
162 {
163 uint32_t reg_val;
164 uint16_t remap;
165
166 remap = (uint16_t)STM32_DT_PINMUX_REMAP(pins[0].pinmux);
167
168 /* not remappable */
169 if (remap == NO_REMAP) {
170 return 0;
171 }
172
173 for (size_t i = 1U; i < pin_cnt; i++) {
174 if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
175 return -EINVAL;
176 }
177 }
178
179 /* A valid remapping configuration is available */
180 /* Apply remapping before proceeding with pin configuration */
181 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
182
183 if (STM32_REMAP_REG_GET(remap) == 0U) {
184 /* read initial value, ignore write-only SWJ_CFG */
185 reg_val = AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG;
186 reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
187 /* apply undocumented '111' (AFIO_MAPR_SWJ_CFG) to affirm SWJ_CFG */
188 /* the pins are not remapped without that (when SWJ_CFG is not default) */
189 AFIO->MAPR = reg_val | AFIO_MAPR_SWJ_CFG;
190 } else {
191 reg_val = AFIO->MAPR2;
192 reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
193 AFIO->MAPR2 = reg_val;
194 }
195
196 return 0;
197 }
198
199 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
200
stm32_pin_configure(uint32_t pin,uint32_t pin_cgf,uint32_t pin_func)201 static int stm32_pin_configure(uint32_t pin, uint32_t pin_cgf, uint32_t pin_func)
202 {
203 const struct device *port_device;
204
205 if (STM32_PORT(pin) >= gpio_ports_cnt) {
206 return -EINVAL;
207 }
208
209 port_device = gpio_ports[STM32_PORT(pin)];
210
211 if ((port_device == NULL) || (!device_is_ready(port_device))) {
212 return -ENODEV;
213 }
214
215 return gpio_stm32_configure(port_device, STM32_PIN(pin), pin_cgf, pin_func);
216 }
217
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)218 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
219 uintptr_t reg)
220 {
221 uint32_t pin, mux;
222 uint32_t pin_cgf = 0;
223 int ret = 0;
224
225 ARG_UNUSED(reg);
226
227 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
228 ret = stm32_pins_remap(pins, pin_cnt);
229 if (ret < 0) {
230 return ret;
231 }
232 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
233
234 for (uint8_t i = 0U; i < pin_cnt; i++) {
235 mux = pins[i].pinmux;
236
237 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
238 uint32_t pupd;
239
240 if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) {
241 pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC;
242 } else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) {
243 pin_cgf = pins[i].pincfg | STM32_MODE_INPUT | STM32_CNF_IN_ANALOG;
244 } else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) {
245 pin_cgf = pins[i].pincfg | STM32_MODE_INPUT;
246 pupd = pin_cgf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
247 if (pupd == STM32_PUPD_NO_PULL) {
248 pin_cgf = pin_cgf | STM32_CNF_IN_FLOAT;
249 } else {
250 pin_cgf = pin_cgf | STM32_CNF_IN_PUPD;
251 }
252 } else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_OUT) {
253 pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT;
254 } else {
255 /* Not supported */
256 __ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
257 }
258 #else
259 if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) {
260 pin_cgf = pins[i].pincfg | STM32_MODER_ALT_MODE;
261 } else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
262 pin_cgf = STM32_MODER_ANALOG_MODE;
263 } else if (STM32_DT_PINMUX_FUNC(mux) == STM32_GPIO) {
264 pin_cgf = pins[i].pincfg;
265 } else {
266 /* Not supported */
267 __ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
268 }
269 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
270
271 pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
272 STM32_DT_PINMUX_LINE(mux));
273
274 ret = stm32_pin_configure(pin, pin_cgf, STM32_DT_PINMUX_FUNC(mux));
275 if (ret < 0) {
276 return ret;
277 }
278 }
279
280 return 0;
281 }
282
