1 /* 2 * Copyright 2022, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/drivers/pinctrl.h> 8 #include <zephyr/init.h> 9 10 #if !defined(CONFIG_SOC_SERIES_LPC11U6X) 11 #include <fsl_clock.h> 12 #endif 13 14 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) 15 #define TYPE(mux) (((mux) & 0xC0000) >> 18) 16 17 #define IOCON_TYPE_D 0x0 18 #define IOCON_TYPE_I 0x1 19 #define IOCON_TYPE_A 0x2 20 21 static volatile uint32_t *iocon = 22 (volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon)); 23 pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)24int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, 25 uintptr_t reg) 26 { 27 for (uint8_t i = 0; i < pin_cnt; i++) { 28 uint32_t pin_mux = pins[i]; 29 uint32_t offset = OFFSET(pin_mux); 30 31 /* Check if this is an analog or i2c type pin */ 32 switch (TYPE(pin_mux)) { 33 case IOCON_TYPE_D: 34 pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK; 35 break; 36 case IOCON_TYPE_I: 37 pin_mux &= Z_PINCTRL_IOCON_I_PIN_MASK; 38 break; 39 case IOCON_TYPE_A: 40 pin_mux &= Z_PINCTRL_IOCON_A_PIN_MASK; 41 break; 42 default: 43 /* Should not occur */ 44 __ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A); 45 } 46 /* Set pinmux */ 47 *(iocon + offset) = pin_mux; 48 } 49 return 0; 50 } 51 52 #if defined(CONFIG_SOC_FAMILY_LPC) && !defined(CONFIG_SOC_SERIES_LPC11U6X) 53 /* LPC family (except 11u6x) needs iocon clock to be enabled */ 54 pinctrl_clock_init(void)55static int pinctrl_clock_init(void) 56 { 57 /* Enable IOCon clock */ 58 CLOCK_EnableClock(kCLOCK_Iocon); 59 return 0; 60 } 61 62 SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); 63 64 #endif /* CONFIG_SOC_FAMILY_LPC && !CONFIG_SOC_SERIES_LPC11U6X */ 65
