1 /*
2 * Copyright (c) 2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/arch/cpu.h>
8 #include <zephyr/init.h>
9 #include <zephyr/drivers/pinctrl.h>
10
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)11 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
12 uintptr_t reg)
13 {
14 /* configure all pins */
15 for (uint8_t i = 0U; i < pin_cnt; i++) {
16 uint32_t mux_register = pins[i].pinmux.mux_register;
17 uint32_t mux_mode = pins[i].pinmux.mux_mode;
18 uint32_t input_register = pins[i].pinmux.input_register;
19 uint32_t input_daisy = pins[i].pinmux.input_daisy;
20 uint32_t config_register = pins[i].pinmux.config_register;
21 uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
22 #if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX)
23 volatile uint32_t *gpr_register =
24 (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register);
25 if (gpr_register) {
26 /* Set or clear specified GPR bit for this mux */
27 if (pins[i].pinmux.gpr_val) {
28 *gpr_register |=
29 (pins[i].pinmux.gpr_val << pins[i].pinmux.gpr_shift);
30 } else {
31 *gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
32 }
33 }
34 #endif
35
36 #ifdef CONFIG_SOC_MIMX93_A55
37 sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
38 IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
39 (mem_addr_t)mux_register);
40 if (input_register) {
41 sys_write32(IOMUXC1_SELECT_INPUT_DAISY(input_daisy),
42 (mem_addr_t)input_register);
43 }
44 if (config_register) {
45 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
46 (mem_addr_t)config_register);
47 }
48 #else
49 sys_write32(
50 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
51 IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
52 (mem_addr_t)mux_register);
53 if (input_register) {
54 sys_write32(IOMUXC_SELECT_INPUT_DAISY(input_daisy),
55 (mem_addr_t)input_register);
56 }
57 if (config_register) {
58 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
59 config_register);
60 }
61 #endif
62 }
63 return 0;
64 }
65
imx_pinctrl_init(void)66 static int imx_pinctrl_init(void)
67 {
68 #ifdef CONFIG_SOC_SERIES_IMX_RT
69 CLOCK_EnableClock(kCLOCK_Iomuxc);
70 #ifdef CONFIG_SOC_SERIES_IMX_RT10XX
71 CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
72 CLOCK_EnableClock(kCLOCK_IomuxcGpr);
73 #elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
74 CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
75 #endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
76 #elif defined(CONFIG_SOC_MIMX8MQ6)
77 CLOCK_EnableClock(kCLOCK_Iomux);
78 #endif /* CONFIG_SOC_SERIES_IMX_RT */
79
80 return 0;
81 }
82
83 SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);
84
