1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_H_ 9 10 #include <soc.h> 11 #include <zephyr/sys/util.h> 12 13 #include "pcie_ep_iproc_regs.h" 14 15 #define PCIE_LINK_STATUS_CONTROL 0xbc 16 #define PCIE_LINKSPEED_SHIFT 16 17 #define PCIE_LINKWIDTH_SHIFT 20 18 #define PCIE_LINKSPEED_MASK 0xf 19 #define PCIE_LINKWIDTH_MASK 0x3f 20 #define PCIE_RC_MODE_MASK 0x1 21 22 #define MSI_ADDR_L 0x5c 23 #define MSI_ADDR_H 0x60 24 #define MSI_DATA 0x64 25 26 #define MSI_COUNT_SHIFT 12 27 #define MSI_COUNT_MASK 0x7000 28 #define MSI_COUNT_VAL 4 29 30 #define MSI_CSR_MASK 0xffffffff 31 #define MSI_EN_MASK 0xf 32 33 #define MSIX_CAP 0xa0 34 #define MSIX_FUNC_MASK BIT(30) 35 36 #define ID_VAL4_OFFSET 0x440 37 #define MSIX_CONTROL 0x4c0 38 #define MSIX_TBL_OFF_BIR 0x4c4 39 #define MSIX_PBA_OFF_BIR 0x4c8 40 41 #define MSIX_TBL_B2_10000 0x10002 42 #define MSIX_PBA_B2_10800 0x10802 43 44 #define MSIX_TABLE_BASE 0x20010000 45 #define MSIX_TABLE_SIZE 16 /* we support 16 MSI-X */ 46 #define MSIX_TBL_ENTRY_SIZE 16 47 #define MSIX_TBL_ADDR_OFF 0 48 #define MSIX_TBL_DATA_OFF 8 49 #define MSIX_TBL_VECTOR_CTRL_OFF 12 50 #define MSIX_VECTOR_MASK BIT(0) 51 #define MSIX_VECTOR_OFF(x) (MSIX_TABLE_BASE + \ 52 (MSIX_TBL_ENTRY_SIZE * (x))) 53 54 #define PBA_TABLE_BASE 0x20010800 55 #define PBA_TABLE_SIZE 0x800 56 #define PBA_OFFSET(x) (PBA_TABLE_BASE + (4 * ((x) / 32))) 57 #define PENDING_BIT(x) ((x) % 32) 58 59 #define PAXB_OARR_VALID BIT(0) 60 61 #ifdef CONFIG_PCIE_EP_IPROC_V2 62 63 #define SNOOP_VALID_INTR BIT(3) 64 #define SNOOP_ADDR1_EN BIT(31) 65 #define SNOOP_ADDR1_MASK 0x1fff 66 #define SNOOP_ADDR1 MSIX_CAP 67 68 #define PMON_LITE_PCIE_INTERRUPT_ENABLE (PMON_LITE_PCIE_BASE + 0xc) 69 #define PMON_LITE_PCIE_INTERRUPT_STATUS (PMON_LITE_PCIE_BASE + 0x10) 70 #define PMON_LITE_PCIE_INTERRUPT_CLEAR (PMON_LITE_PCIE_BASE + 0x14) 71 #define WR_ADDR_CHK_INTR_EN 2 72 73 #define PMON_LITE_PCIE_AXI_FILTER_0_CONTROL (PMON_LITE_PCIE_BASE + 0xd4) 74 #define AXI_FILTER_0_ENABLE (BIT(30) | BIT(2) | \ 75 BIT(1) | BIT(0)) 76 77 #define AXI_FILTER_0_ADDR_START_LOW (PMON_LITE_PCIE_BASE + 0xd8) 78 #define AXI_FILTER_0_ADDR_START_HIGH (PMON_LITE_PCIE_BASE + 0xdc) 79 #define AXI_FILTER_0_ADDR_END_LOW (PMON_LITE_PCIE_BASE + 0xe0) 80 #define AXI_FILTER_0_ADDR_END_HIGH (PMON_LITE_PCIE_BASE + 0xe4) 81 82 #endif 83 84 #define PCIE_DEV_CTRL_OFFSET 0x4d8 85 #define FLR_IN_PROGRESS BIT(27) 86 87 #define PCIE_TL_CTRL0_OFFSET 0x800 88 #define AUTO_CLR_FLR_AFTER_DELAY BIT(13) /* Clears FLR after 55ms */ 89 #define AUTO_CLR_CRS_POST_FLR BIT(14) 90 91 #define PCIE0_FLR_INTR BIT(20) 92 #define PCIE0_FLR_PERST_INTR BIT(21) 93 94 enum pcie_outbound_map { 95 PCIE_MAP_LOWMEM_IDX, 96 PCIE_MAP_HIGHMEM_IDX, 97 }; 98 99 struct iproc_pcie_ep_config { 100 struct iproc_pcie_reg *base; /* Base address of PAXB registers */ 101 uint32_t reg_size; 102 uint32_t map_low_base; /* Base addr of outbound mapping at lowmem */ 103 uint32_t map_low_size; 104 uint64_t map_high_base; /* Base addr of outbound mapping at highmem */ 105 uint32_t map_high_size; 106 unsigned int id; 107 const struct device *pl330_dev; 108 uint32_t pl330_tx_chan_id; /* channel used for Device to Host write */ 109 uint32_t pl330_rx_chan_id; /* channel used for Host to Device read */ 110 }; 111 112 struct iproc_pcie_ep_ctx { 113 struct k_spinlock ob_map_lock; 114 struct k_spinlock raise_irq_lock; 115 struct k_spinlock pba_lock; 116 bool highmem_in_use; 117 bool lowmem_in_use; 118 /* Callback function for reset interrupt */ 119 pcie_ep_reset_callback_t reset_cb[PCIE_RESET_MAX]; 120 /* Callback data for reset interrupt */ 121 void *reset_data[PCIE_RESET_MAX]; 122 }; 123 124 void iproc_pcie_msix_config(const struct device *dev); 125 void iproc_pcie_msi_config(const struct device *dev); 126 127 int iproc_pcie_generate_msi(const struct device *dev, const uint32_t msi_num); 128 int iproc_pcie_generate_msix(const struct device *dev, const uint32_t msix_num); 129 130 void iproc_pcie_func_mask_isr(void *arg); 131 void iproc_pcie_vector_mask_isr(void *arg); 132 133 #endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_H_ */ 134
