1 /*
2 * Copyright (c) 2014 Wind River Systems, Inc.
3 * Copyright (c) 2020-2022 Synopsys.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @file
10 * @brief ARCv2 Interrupt Unit device driver
11 *
12 * The ARCv2 interrupt unit has 16 allocated exceptions associated with
13 * vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
14 * The interrupt unit is optional in the ARCv2-based processors. When
15 * building a processor, you can configure the processor to include an
16 * interrupt unit. The ARCv2 interrupt unit is highly programmable.
17 */
18
19 #include <zephyr/kernel.h>
20 #include <zephyr/arch/cpu.h>
21 #include <zephyr/device.h>
22 #include <zephyr/device.h>
23
24 #define DT_DRV_COMPAT snps_arcv2_intc
25
26 #ifdef CONFIG_ARC_CONNECT
arc_shared_intc_init(void)27 static void arc_shared_intc_init(void)
28 {
29 /*
30 * Initialize all IDU interrupts:
31 * - select round-robbin
32 * - disable all lines
33 */
34 BUILD_ASSERT(CONFIG_NUM_IRQS > ARC_CONNECT_IDU_IRQ_START);
35 __ASSERT(z_arc_v2_core_id() == ARC_MP_PRIMARY_CPU_ID,
36 "idu interrupts must be inited from primary core");
37
38 z_arc_connect_idu_disable();
39
40 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
41 /*
42 * TODO: don't use z_arc_connect_idu* functions to avoid
43 * locking/unlocking every time.
44 */
45
46 /* Disable (mask) line */
47 z_arc_connect_idu_set_mask(i, 0x1);
48 z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL,
49 ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN);
50
51 /*
52 * Fake round-robin: we allow to distribute interrupts only to primary core as
53 * secondary cores may be not initialized yet.
54 */
55 z_arc_connect_idu_set_dest(i, BIT(ARC_MP_PRIMARY_CPU_ID));
56 }
57
58 z_arc_connect_idu_enable();
59
60 }
61
62 /* Allow to schedule IRQ to all cores after we bring up all secondary cores */
arc_shared_intc_update_post_smp(void)63 static int arc_shared_intc_update_post_smp(void)
64 {
65 __ASSERT(z_arc_v2_core_id() == ARC_MP_PRIMARY_CPU_ID,
66 "idu interrupts must be updated from primary core");
67
68 z_arc_connect_idu_disable();
69
70 for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
71 /* TODO: take arc_connect_spinlock one time to avoid locking/unlocking every time */
72 z_arc_connect_idu_set_dest(i, BIT_MASK(arch_num_cpus()));
73 }
74
75 z_arc_connect_idu_enable();
76
77 return 0;
78 }
79
80 SYS_INIT(arc_shared_intc_update_post_smp, SMP, 0);
81 #endif /* CONFIG_ARC_CONNECT */
82
83
84 /* lowest IRQ priority */
85 #ifdef CONFIG_ARC_SECURE_FIRMWARE
86 #define ARC_IRQ_DEFAULT_PRIORITY ((CONFIG_NUM_IRQ_PRIO_LEVELS - 1) | _ARC_V2_IRQ_PRIORITY_SECURE)
87 #else
88 #define ARC_IRQ_DEFAULT_PRIORITY (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
89 #endif
90
arc_core_intc_init_nolock(uint32_t irq,uint32_t state)91 static inline void arc_core_intc_init_nolock(uint32_t irq, uint32_t state)
92 {
93 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
94 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, ARC_IRQ_DEFAULT_PRIORITY);
95 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, _ARC_V2_INT_LEVEL);
96 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, state);
97 }
98
99 /*
100 * Initialize the core private interrupt controller.
101 *
102 * This function must be called on each CPU in case of SMP system.
103 *
104 * NOTE: core interrupts are still globally disabled at this point (STATUS32.IE = 0), so there is
105 * no need to protect the window between a write to IRQ_SELECT and subsequent writes to the
106 * selected IRQ's registers with locks.
107 */
arc_core_private_intc_init(void)108 void arc_core_private_intc_init(void)
109 {
110 /*
111 * Interrupts from 0 to 15 are exceptions and they are ignored by IRQ auxiliary registers.
112 * We skip those interrupt lines while setting up core private interrupt controller.
113 */
114 BUILD_ASSERT(CONFIG_GEN_IRQ_START_VECTOR == 16);
115
116 /*
117 * System with IDU case (most likely multi-core system):
118 * - disable private IRQs: they will be enabled with irq_enable before usage
119 * - enable shared (IDU) IRQs: their enabling / disabling is controlled via IDU, so we
120 * always pass them via core private interrupt controller.
121 * System without IDU case (single-core system):
122 * - disable all IRQs: they will be enabled with irq_enable before usage
123 */
124 #ifdef CONFIG_ARC_CONNECT
125 for (uint32_t irq = CONFIG_GEN_IRQ_START_VECTOR; irq < ARC_CONNECT_IDU_IRQ_START; irq++) {
126 arc_core_intc_init_nolock(irq, _ARC_V2_INT_DISABLE);
127 }
128
129 for (uint32_t irq = ARC_CONNECT_IDU_IRQ_START; irq < CONFIG_NUM_IRQS; irq++) {
130 arc_core_intc_init_nolock(irq, _ARC_V2_INT_ENABLE);
131 }
132 #else
133 for (uint32_t irq = CONFIG_GEN_IRQ_START_VECTOR; irq < CONFIG_NUM_IRQS; irq++) {
134 arc_core_intc_init_nolock(irq, _ARC_V2_INT_DISABLE);
135 }
136 #endif /* CONFIG_ARC_CONNECT */
137 }
138
arc_irq_init(const struct device * dev)139 static int arc_irq_init(const struct device *dev)
140 {
141 #ifdef CONFIG_ARC_CONNECT
142 arc_shared_intc_init();
143 #endif /* CONFIG_ARC_CONNECT */
144
145 /*
146 * We initialize per-core part for core 0 here,
147 * for rest cores it will be initialized in slave_start.
148 */
149 arc_core_private_intc_init();
150
151 return 0;
152 }
153
154 DEVICE_DT_INST_DEFINE(0, arc_irq_init, NULL, NULL, NULL,
155 PRE_KERNEL_1, 0, NULL);
156
