1 /*
2 * Copyright (c) 2017 Piotr Mienkowski
3 * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT atmel_sam_i2c_twim
9
10 /** @file
11 * @brief I2C bus (TWIM) driver for Atmel SAM4L MCU family.
12 *
13 * I2C Master Mode with 7/10 bit addressing is currently supported.
14 * Very long transfers are allowed using NCMDR register. DMA is not
15 * yet supported.
16 */
17
18 #include <errno.h>
19 #include <zephyr/sys/__assert.h>
20 #include <zephyr/kernel.h>
21 #include <zephyr/device.h>
22 #include <zephyr/init.h>
23 #include <soc.h>
24 #include <zephyr/drivers/i2c.h>
25 #include <zephyr/drivers/pinctrl.h>
26 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
27
28 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
29 #include <zephyr/logging/log.h>
30 #include <zephyr/irq.h>
31 LOG_MODULE_REGISTER(i2c_sam_twim);
32
33 #include "i2c-priv.h"
34
35 /** I2C bus speed [Hz] in Standard Mode */
36 #define BUS_SPEED_STANDARD_HZ 100000U
37 /** I2C bus speed [Hz] in Fast Mode */
38 #define BUS_SPEED_FAST_HZ 400000U
39 /** I2C bus speed [Hz] in Fast Plus Mode */
40 #define BUS_SPEED_PLUS_HZ 1000000U
41 /** I2C bus speed [Hz] in High Speed Mode */
42 #define BUS_SPEED_HIGH_HZ 3400000U
43 /* Maximum value of Clock Divider (CKDIV) */
44 #define CKDIV_MAX 7
45 /* Maximum Frequency prescaled */
46 #define F_PRESCALED_MAX 255
47
48 /** Status Clear Register Mask for No Acknowledgements */
49 #define TWIM_SCR_NAK_MASK (TWIM_SCR_ANAK | TWIM_SCR_DNAK)
50 /** Status Register Mask for No Acknowledgements */
51 #define TWIM_SR_NAK_MASK (TWIM_SR_ANAK | TWIM_SR_DNAK)
52 /** Interrupt Enable Register Mask for No Acknowledgements */
53 #define TWIM_IER_NAK_MASK (TWIM_IER_ANAK | TWIM_IER_DNAK)
54 /** Frequently used Interrupt Enable Register Mask */
55 #define TWIM_IER_STD_MASK (TWIM_IER_ANAK | TWIM_IER_ARBLST)
56 /** Frequently used Status Clear Register Mask */
57 #define TWIM_SR_STD_MASK (TWIM_SR_ANAK | TWIM_SR_ARBLST)
58
59 /** \internal Max value of NBYTES per transfer by hardware */
60 #define TWIM_MAX_NBYTES_PER_XFER \
61 (TWIM_CMDR_NBYTES_Msk >> TWIM_CMDR_NBYTES_Pos)
62
63 #define TWIM_NCMDR_FREE_WAIT 2000
64
65 /* Device constant configuration parameters */
66 struct i2c_sam_twim_dev_cfg {
67 Twim *regs;
68 void (*irq_config)(void);
69 uint32_t bitrate;
70 const struct atmel_sam_pmc_config clock_cfg;
71 const struct pinctrl_dev_config *pcfg;
72 uint8_t irq_id;
73
74 uint8_t std_clk_slew_lim;
75 uint8_t std_clk_strength_low;
76 uint8_t std_data_slew_lim;
77 uint8_t std_data_strength_low;
78 uint8_t hs_clk_slew_lim;
79 uint8_t hs_clk_strength_high;
80 uint8_t hs_clk_strength_low;
81 uint8_t hs_data_slew_lim;
82 uint8_t hs_data_strength_low;
83
84 uint8_t hs_master_code;
85 };
86
87 /* Device run time data */
88 struct i2c_sam_twim_dev_data {
89 struct k_mutex bus_mutex;
90 struct k_sem sem;
91
92 struct i2c_msg *msgs;
93 uint32_t msg_cur_idx;
94 uint32_t msg_next_idx;
95 uint32_t msg_max_idx;
96
97 uint32_t cur_remaining;
98 uint32_t cur_idx;
99 uint32_t cur_sr;
100
101 uint32_t next_nb_bytes;
102 bool next_is_valid;
103 bool next_need_rs;
104 bool cur_need_rs;
105 };
106
i2c_clk_set(const struct device * dev,uint32_t speed)107 static int i2c_clk_set(const struct device *dev, uint32_t speed)
108 {
109 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config;
110 Twim *const twim = cfg->regs;
111 uint32_t per_clk = SOC_ATMEL_SAM_MCK_FREQ_HZ;
112 uint32_t f_prescaled = (per_clk / speed / 2);
113 uint32_t cwgr_reg_val = 0;
114 uint8_t cwgr_exp = 0;
115
116 /* f_prescaled must fit in 8 bits, cwgr_exp must fit in 3 bits */
117 while ((f_prescaled > F_PRESCALED_MAX) && (cwgr_exp <= CKDIV_MAX)) {
118 /* increase clock divider */
119 cwgr_exp++;
120 /* divide f_prescaled value */
121 f_prescaled /= 2;
122 }
123
124 if (cwgr_exp > CKDIV_MAX) {
125 LOG_ERR("Failed to configure I2C clock");
126 return -EIO;
127 }
128
129 cwgr_reg_val = TWIM_HSCWGR_LOW(f_prescaled / 2) |
130 TWIM_HSCWGR_HIGH(f_prescaled -
131 (f_prescaled / 2)) |
132 TWIM_HSCWGR_EXP(cwgr_exp) |
133 TWIM_HSCWGR_DATA(0) |
134 TWIM_HSCWGR_STASTO(f_prescaled);
135
136 /* This configuration should be applied after a TWIM_CR_SWRST
137 * Set clock waveform generator register
138 */
139 if (speed == BUS_SPEED_HIGH_HZ) {
140 twim->HSCWGR = cwgr_reg_val;
141 } else {
142 twim->CWGR = cwgr_reg_val;
143 }
144
145 LOG_DBG("per_clk: %d, f_prescaled: %d, cwgr_exp: 0x%02x,"
146 "cwgr_reg_val: 0x%08x", per_clk, f_prescaled,
147 cwgr_exp, cwgr_reg_val);
148
149 /* Set clock and data slew rate */
150 twim->SRR = ((speed == BUS_SPEED_PLUS_HZ) ? TWIM_SRR_FILTER(2) :
151 TWIM_SRR_FILTER(3)) |
152 TWIM_SRR_CLSLEW(cfg->std_clk_slew_lim) |
153 TWIM_SRR_CLDRIVEL(cfg->std_clk_strength_low) |
154 TWIM_SRR_DASLEW(cfg->std_data_slew_lim) |
155 TWIM_SRR_DADRIVEL(cfg->std_data_strength_low);
156
157 twim->HSSRR = TWIM_HSSRR_FILTER(1) |
158 TWIM_HSSRR_CLSLEW(cfg->hs_clk_slew_lim) |
159 TWIM_HSSRR_CLDRIVEH(cfg->hs_clk_strength_high) |
160 TWIM_HSSRR_CLDRIVEL(cfg->hs_clk_strength_low) |
161 TWIM_HSSRR_DASLEW(cfg->hs_data_slew_lim) |
162 TWIM_HSSRR_DADRIVEL(cfg->hs_data_strength_low);
163
164 return 0;
165 }
166
i2c_sam_twim_configure(const struct device * dev,uint32_t config)167 static int i2c_sam_twim_configure(const struct device *dev, uint32_t config)
168 {
169 uint32_t bitrate;
170 int ret;
171
172 if (!(config & I2C_MODE_CONTROLLER)) {
173 LOG_ERR("Master Mode is not enabled");
174 return -EIO;
175 }
176
177 if (config & I2C_ADDR_10_BITS) {
178 LOG_ERR("I2C 10-bit addressing is currently not supported");
179 LOG_ERR("Please submit a patch");
180 return -EIO;
181 }
182
183 /* Configure clock */
184 switch (I2C_SPEED_GET(config)) {
185 case I2C_SPEED_STANDARD:
186 bitrate = BUS_SPEED_STANDARD_HZ;
187 break;
188 case I2C_SPEED_FAST:
189 bitrate = BUS_SPEED_FAST_HZ;
190 break;
191 case I2C_SPEED_FAST_PLUS:
192 bitrate = BUS_SPEED_PLUS_HZ;
193 break;
194 case I2C_SPEED_HIGH:
195 bitrate = BUS_SPEED_HIGH_HZ;
196 break;
197 default:
198 LOG_ERR("Unsupported I2C speed value");
199 return -EIO;
200 }
201
202 /* Setup clock waveform */
203 ret = i2c_clk_set(dev, bitrate);
204 if (ret < 0) {
205 return ret;
206 }
207
208 return 0;
209 }
210
i2c_prepare_xfer_data(struct i2c_sam_twim_dev_data * data)211 static void i2c_prepare_xfer_data(struct i2c_sam_twim_dev_data *data)
212 {
213 struct i2c_msg *next_msg = NULL;
214
215 if (data->next_nb_bytes > TWIM_MAX_NBYTES_PER_XFER) {
216 data->cur_remaining = TWIM_MAX_NBYTES_PER_XFER;
217
218 data->next_nb_bytes -= TWIM_MAX_NBYTES_PER_XFER;
219 data->next_is_valid = true;
220 data->next_need_rs = false;
221 } else {
222 data->cur_remaining = data->next_nb_bytes;
223
224 if ((data->msg_next_idx + 1) < data->msg_max_idx) {
225 next_msg = &data->msgs[++data->msg_next_idx];
226
227 data->next_nb_bytes = next_msg->len;
228 data->next_is_valid = true;
229 data->next_need_rs = true;
230 } else {
231 data->next_nb_bytes = 0;
232 data->next_is_valid = false;
233 data->next_need_rs = false;
234 }
235 }
236 }
237
i2c_prepare_xfer_cmd(struct i2c_sam_twim_dev_data * data,uint32_t * cmdr_reg,uint32_t next_msg_idx)238 static uint32_t i2c_prepare_xfer_cmd(struct i2c_sam_twim_dev_data *data,
239 uint32_t *cmdr_reg,
240 uint32_t next_msg_idx)
241 {
242 struct i2c_msg *next_msg = &data->msgs[next_msg_idx];
243 bool next_msg_is_read;
244 uint32_t next_nb_remaining;
245
246 *cmdr_reg &= ~(TWIM_CMDR_NBYTES_Msk |
247 TWIM_CMDR_ACKLAST |
248 TWIM_CMDR_START |
249 TWIM_CMDR_READ);
250
251 next_msg_is_read = ((next_msg->flags & I2C_MSG_RW_MASK) ==
252 I2C_MSG_READ);
253
254 if (next_msg_is_read) {
255 *cmdr_reg |= TWIM_CMDR_READ;
256 }
257
258 if (data->next_need_rs) {
259 /* TODO: evaluate 10 bits repeat start read
260 * because of blank cmd
261 */
262 *cmdr_reg |= TWIM_CMDR_START;
263 }
264
265 if (data->next_nb_bytes > TWIM_MAX_NBYTES_PER_XFER) {
266 next_nb_remaining = TWIM_MAX_NBYTES_PER_XFER;
267
268 if (next_msg_is_read) {
269 *cmdr_reg |= TWIM_CMDR_ACKLAST;
270 }
271 } else {
272 next_nb_remaining = data->next_nb_bytes;
273
274 /* Is there any more messages ? */
275 if ((next_msg_idx + 1) >= data->msg_max_idx) {
276 *cmdr_reg |= TWIM_CMDR_STOP;
277 }
278 }
279
280 return next_nb_remaining;
281 }
282
i2c_start_xfer(const struct device * dev,uint16_t daddr)283 static void i2c_start_xfer(const struct device *dev, uint16_t daddr)
284 {
285 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config;
286 struct i2c_sam_twim_dev_data *data = dev->data;
287 struct i2c_msg *msg = &data->msgs[0];
288 Twim *const twim = cfg->regs;
289 uint32_t cmdr_reg;
290 uint32_t data_size;
291 uint32_t cur_is_read;
292
293 /* Reset the TWIM module */
294 twim->CR = TWIM_CR_MEN;
295 twim->CR = TWIM_CR_SWRST;
296 twim->CR = TWIM_CR_MDIS;
297 twim->IDR = ~0UL; /* Clear the interrupt flags */
298 twim->SCR = ~0UL; /* Clear the status flags */
299
300 /* Reset indexes */
301 data->msg_cur_idx = 0;
302 data->msg_next_idx = 0;
303
304 /* pre-load current message to infer next */
305 data->next_nb_bytes = data->msgs[data->msg_next_idx].len;
306 data->next_is_valid = false;
307 data->next_need_rs = false;
308 data->cur_remaining = 0;
309 data->cur_idx = 0;
310
311 LOG_DBG("Config first/next Transfer: msgs: %d", data->msg_max_idx);
312
313 cmdr_reg = TWIM_CMDR_SADR(daddr) |
314 TWIM_CMDR_VALID;
315
316 if (I2C_SPEED_GET(msg->flags) >= I2C_SPEED_HIGH) {
317 cmdr_reg |= TWIM_CMDR_HS |
318 TWIM_CMDR_HSMCODE(cfg->hs_master_code);
319 }
320
321 if (msg->flags & I2C_MSG_ADDR_10_BITS) {
322 cmdr_reg |= TWIM_CMDR_TENBIT;
323 }
324
325 if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ &&
326 (msg->flags & I2C_MSG_ADDR_10_BITS)) {
327
328 /* Fill transfer command (empty)
329 * It must be a write xfer with NBYTES = 0
330 */
331 twim->CMDR = cmdr_reg | TWIM_CMDR_START;
332
333 /* Fill next transfer command. REPSAME performs a repeated
334 * start to the same slave address as addressed in the
335 * previous transfer in order to enter master receiver mode.
336 */
337 cmdr_reg |= TWIM_CMDR_REPSAME;
338
339 i2c_prepare_xfer_data(data);
340
341 /* Special condition: reset msg_next_idx */
342 data->msg_next_idx = 0;
343
344 data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, 0);
345 cmdr_reg |= TWIM_CMDR_NBYTES(data->cur_remaining);
346 twim->NCMDR = cmdr_reg | TWIM_CMDR_START;
347 } else {
348 /* Fill transfer command */
349 i2c_prepare_xfer_data(data);
350
351 data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, 0);
352 cmdr_reg |= TWIM_CMDR_NBYTES(data->cur_remaining);
353 twim->CMDR = cmdr_reg | TWIM_CMDR_START;
354
355 /* Fill next transfer command */
356 if (data->next_is_valid) {
357 data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg,
358 data->msg_next_idx);
359 cmdr_reg |= TWIM_CMDR_NBYTES(data_size);
360 twim->NCMDR = cmdr_reg;
361 }
362 }
363
364 LOG_DBG("Start Transfer: CMDR: 0x%08x, NCMDR: 0x%08x",
365 twim->CMDR, twim->NCMDR);
366
367 /* Extract Read/Write start operation */
368 cmdr_reg = twim->CMDR;
369 cur_is_read = (cmdr_reg & TWIM_CMDR_READ);
370
371 /* Enable master transfer */
372 twim->CR = TWIM_CR_MEN;
373
374 twim->IER = TWIM_IER_STD_MASK |
375 (cur_is_read ? TWIM_IER_RXRDY : TWIM_IER_TXRDY) |
376 TWIM_IER_IDLE;
377 }
378
i2c_prepare_next(struct i2c_sam_twim_dev_data * data,Twim * const twim)379 static void i2c_prepare_next(struct i2c_sam_twim_dev_data *data,
380 Twim *const twim)
381 {
382 struct i2c_msg *msg = &data->msgs[data->msg_cur_idx];
383 volatile uint32_t ncmdr_wait;
384 uint32_t cmdr_reg;
385 uint32_t data_size;
386 uint32_t cur_is_read;
387
388 if (data->cur_idx == msg->len) {
389 data->cur_idx = 0;
390 data->msg_cur_idx++;
391 }
392
393 i2c_prepare_xfer_data(data);
394
395 /* Sync CMDR with NCMDR before apply changes */
396 ncmdr_wait = TWIM_NCMDR_FREE_WAIT;
397 while ((twim->NCMDR & TWIM_NCMDR_VALID) && (ncmdr_wait--)) {
398 ;
399 }
400
401 cmdr_reg = twim->CMDR;
402 cur_is_read = (cmdr_reg & TWIM_CMDR_READ);
403 twim->IER |= (cur_is_read ? TWIM_IER_RXRDY : TWIM_IER_TXRDY);
404
405 /* Is there any more transfer? */
406 if (data->next_nb_bytes == 0) {
407 return;
408 }
409
410 data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, data->msg_next_idx);
411 cmdr_reg |= TWIM_CMDR_NBYTES(data_size);
412 twim->NCMDR = cmdr_reg;
413
414 LOG_DBG("ld xfer: NCMDR: 0x%08x", twim->NCMDR);
415 }
416
i2c_sam_twim_isr(const struct device * dev)417 static void i2c_sam_twim_isr(const struct device *dev)
418 {
419 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config;
420 struct i2c_sam_twim_dev_data *const data = dev->data;
421 Twim *const twim = cfg->regs;
422 struct i2c_msg *msg = &data->msgs[data->msg_cur_idx];
423 uint32_t isr_status;
424
425 /* Retrieve interrupt status */
426 isr_status = twim->SR & twim->IMR;
427
428 LOG_DBG("ISR: IMR: 0x%08x", isr_status);
429
430 /* Not Acknowledged */
431 if (isr_status & TWIM_SR_STD_MASK) {
432 /*
433 * If we get a NACK, clear the valid bit in CMDR,
434 * otherwise the command will be re-sent.
435 */
436 twim->NCMDR &= ~TWIM_NCMDR_VALID;
437 twim->CMDR &= ~TWIM_CMDR_VALID;
438
439 data->cur_sr = isr_status;
440 goto xfer_comp;
441 }
442
443 data->cur_sr = 0;
444
445 /* Byte received */
446 if (isr_status & TWIM_SR_RXRDY) {
447 msg->buf[data->cur_idx++] = twim->RHR;
448 data->cur_remaining--;
449
450 if (data->cur_remaining > 0) {
451 goto check_xfer;
452 }
453
454 twim->IDR = TWIM_IDR_RXRDY;
455
456 /* Check for next transfer */
457 if (data->next_is_valid && data->next_nb_bytes > 0) {
458 i2c_prepare_next(data, twim);
459 } else {
460 data->next_nb_bytes = 0;
461 }
462 }
463
464 /* Byte sent */
465 if (isr_status & TWIM_SR_TXRDY) {
466
467 if (data->cur_idx < msg->len) {
468 twim->THR = msg->buf[data->cur_idx++];
469 data->cur_remaining--;
470
471 goto check_xfer;
472 }
473
474 twim->IDR = TWIM_IDR_TXRDY;
475
476 /* Check for next transfer */
477 if (data->next_is_valid && data->next_nb_bytes > 0) {
478 i2c_prepare_next(data, twim);
479 }
480 }
481
482 check_xfer:
483
484 /* Is transaction finished ? */
485 if (!(isr_status & TWIM_SR_IDLE)) {
486 return;
487 }
488
489 LOG_DBG("ISR: TWIM_SR_IDLE");
490
491 xfer_comp:
492 /* Disable all enabled interrupts */
493 twim->IDR = ~0UL;
494
495 /* Clear all status */
496 twim->SCR = ~0UL;
497
498 /* We are done */
499 k_sem_give(&data->sem);
500 }
501
i2c_sam_twim_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)502 static int i2c_sam_twim_transfer(const struct device *dev,
503 struct i2c_msg *msgs,
504 uint8_t num_msgs, uint16_t addr)
505 {
506 struct i2c_sam_twim_dev_data *data = dev->data;
507 int ret = 0;
508
509 /* Send out messages */
510 k_mutex_lock(&data->bus_mutex, K_FOREVER);
511
512 /* Load messages */
513 data->msgs = msgs;
514 data->msg_max_idx = num_msgs;
515
516 i2c_start_xfer(dev, addr);
517
518 /* Wait for the message transfer to complete */
519 k_sem_take(&data->sem, K_FOREVER);
520
521 if (data->cur_sr & TWIM_SR_STD_MASK) {
522 ret = -EIO;
523
524 LOG_INF("MSG: %d, ANAK: %d, ARBLST: %d",
525 data->msg_cur_idx,
526 (data->cur_sr & TWIM_SR_ANAK) > 0,
527 (data->cur_sr & TWIM_SR_ARBLST) > 0);
528 }
529
530 k_mutex_unlock(&data->bus_mutex);
531
532 return ret;
533 }
534
i2c_sam_twim_initialize(const struct device * dev)535 static int i2c_sam_twim_initialize(const struct device *dev)
536 {
537 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config;
538 struct i2c_sam_twim_dev_data *data = dev->data;
539 Twim *const twim = cfg->regs;
540 uint32_t bitrate_cfg;
541 int ret;
542
543 /* Configure interrupts */
544 cfg->irq_config();
545
546 /*
547 * initialize mutex. it is used when multiple transfers are taking
548 * place to guarantee that each one is atomic and has exclusive access
549 * to the I2C bus.
550 */
551 k_mutex_init(&data->bus_mutex);
552
553 /* Initialize semaphore */
554 k_sem_init(&data->sem, 0, 1);
555
556 /* Connect pins to the peripheral */
557 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
558 if (ret < 0) {
559 return ret;
560 }
561
562 /* Enable TWIM clock in PM */
563 (void)clock_control_on(SAM_DT_PMC_CONTROLLER,
564 (clock_control_subsys_t)&cfg->clock_cfg);
565
566 /* Enable the module*/
567 twim->CR = TWIM_CR_MEN;
568
569 /* Reset the module */
570 twim->CR |= TWIM_CR_SWRST;
571
572 /* Clear SR */
573 twim->SCR = ~0UL;
574
575 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
576
577 ret = i2c_sam_twim_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
578 if (ret < 0) {
579 LOG_ERR("Failed to initialize %s device", dev->name);
580 return ret;
581 }
582
583 /* Enable module's IRQ */
584 irq_enable(cfg->irq_id);
585
586 LOG_INF("Device %s initialized", dev->name);
587
588 return 0;
589 }
590
591 static const struct i2c_driver_api i2c_sam_twim_driver_api = {
592 .configure = i2c_sam_twim_configure,
593 .transfer = i2c_sam_twim_transfer,
594 };
595
596 #define I2C_TWIM_SAM_SLEW_REGS(n) \
597 .std_clk_slew_lim = DT_INST_ENUM_IDX(n, std_clk_slew_lim), \
598 .std_clk_strength_low = DT_INST_ENUM_IDX(n, std_clk_strength_low),\
599 .std_data_slew_lim = DT_INST_ENUM_IDX(n, std_data_slew_lim), \
600 .std_data_strength_low = DT_INST_ENUM_IDX(n, std_data_strength_low),\
601 .hs_clk_slew_lim = DT_INST_ENUM_IDX(n, hs_clk_slew_lim), \
602 .hs_clk_strength_high = DT_INST_ENUM_IDX(n, hs_clk_strength_high),\
603 .hs_clk_strength_low = DT_INST_ENUM_IDX(n, hs_clk_strength_low),\
604 .hs_data_slew_lim = DT_INST_ENUM_IDX(n, hs_data_slew_lim), \
605 .hs_data_strength_low = DT_INST_ENUM_IDX(n, hs_data_strength_low)
606
607 #define I2C_TWIM_SAM_INIT(n) \
608 PINCTRL_DT_INST_DEFINE(n); \
609 static void i2c##n##_sam_irq_config(void) \
610 { \
611 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
612 i2c_sam_twim_isr, \
613 DEVICE_DT_INST_GET(n), 0); \
614 } \
615 \
616 static const struct i2c_sam_twim_dev_cfg i2c##n##_sam_config = {\
617 .regs = (Twim *)DT_INST_REG_ADDR(n), \
618 .irq_config = i2c##n##_sam_irq_config, \
619 .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
620 .irq_id = DT_INST_IRQN(n), \
621 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
622 .bitrate = DT_INST_PROP(n, clock_frequency), \
623 .hs_master_code = DT_INST_ENUM_IDX(n, hs_master_code), \
624 I2C_TWIM_SAM_SLEW_REGS(n), \
625 }; \
626 \
627 static struct i2c_sam_twim_dev_data i2c##n##_sam_data; \
628 \
629 I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twim_initialize, \
630 NULL, \
631 &i2c##n##_sam_data, &i2c##n##_sam_config, \
632 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
633 &i2c_sam_twim_driver_api)
634
635 DT_INST_FOREACH_STATUS_OKAY(I2C_TWIM_SAM_INIT);
636
