1 /*
2 * Copyright (c) 2017, I-SENSE group of ICCS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
8 *
9 */
10
11 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <stm32_ll_i2c.h>
17 #include <errno.h>
18 #include <zephyr/drivers/i2c.h>
19 #include "i2c_ll_stm32.h"
20
21 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ll_stm32_v1);
24
25 #include "i2c-priv.h"
26
27 #define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
28
29 #define STM32_I2C_TIMEOUT_USEC 1000
30 #define I2C_REQUEST_WRITE 0x00
31 #define I2C_REQUEST_READ 0x01
32 #define HEADER 0xF0
33
stm32_i2c_generate_start_condition(I2C_TypeDef * i2c)34 static void stm32_i2c_generate_start_condition(I2C_TypeDef *i2c)
35 {
36 uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1);
37
38 if (cr1 & I2C_CR1_STOP) {
39 LOG_DBG("%s: START while STOP active!", __func__);
40 LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP);
41 }
42
43 LL_I2C_GenerateStartCondition(i2c);
44 }
45
46 #ifdef CONFIG_I2C_STM32_INTERRUPT
47
stm32_i2c_disable_transfer_interrupts(const struct device * dev)48 static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
49 {
50 const struct i2c_stm32_config *cfg = dev->config;
51 I2C_TypeDef *i2c = cfg->i2c;
52
53 LL_I2C_DisableIT_TX(i2c);
54 LL_I2C_DisableIT_RX(i2c);
55 LL_I2C_DisableIT_EVT(i2c);
56 LL_I2C_DisableIT_BUF(i2c);
57 LL_I2C_DisableIT_ERR(i2c);
58 }
59
stm32_i2c_enable_transfer_interrupts(const struct device * dev)60 static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
61 {
62 const struct i2c_stm32_config *cfg = dev->config;
63 I2C_TypeDef *i2c = cfg->i2c;
64
65 LL_I2C_EnableIT_ERR(i2c);
66 LL_I2C_EnableIT_EVT(i2c);
67 LL_I2C_EnableIT_BUF(i2c);
68 }
69
70 #endif /* CONFIG_I2C_STM32_INTERRUPT */
71
stm32_i2c_reset(const struct device * dev)72 static void stm32_i2c_reset(const struct device *dev)
73 {
74 const struct i2c_stm32_config *cfg = dev->config;
75 I2C_TypeDef *i2c = cfg->i2c;
76 uint16_t cr1, cr2, oar1, oar2, trise, ccr;
77 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
78 uint16_t fltr;
79 #endif
80
81 /* disable i2c and disable IRQ's */
82 LL_I2C_Disable(i2c);
83 #ifdef CONFIG_I2C_STM32_INTERRUPT
84 stm32_i2c_disable_transfer_interrupts(dev);
85 #endif
86
87 /* save all important registers before reset */
88 cr1 = LL_I2C_ReadReg(i2c, CR1);
89 cr2 = LL_I2C_ReadReg(i2c, CR2);
90 oar1 = LL_I2C_ReadReg(i2c, OAR1);
91 oar2 = LL_I2C_ReadReg(i2c, OAR2);
92 ccr = LL_I2C_ReadReg(i2c, CCR);
93 trise = LL_I2C_ReadReg(i2c, TRISE);
94 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
95 fltr = LL_I2C_ReadReg(i2c, FLTR);
96 #endif
97
98 /* reset i2c hardware */
99 LL_I2C_EnableReset(i2c);
100 LL_I2C_DisableReset(i2c);
101
102 /* restore all important registers after reset */
103 LL_I2C_WriteReg(i2c, CR1, cr1);
104 LL_I2C_WriteReg(i2c, CR2, cr2);
105
106 /* bit 14 of OAR1 must always be 1 */
107 oar1 |= (1 << 14);
108 LL_I2C_WriteReg(i2c, OAR1, oar1);
109 LL_I2C_WriteReg(i2c, OAR2, oar2);
110 LL_I2C_WriteReg(i2c, CCR, ccr);
111 LL_I2C_WriteReg(i2c, TRISE, trise);
112 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
113 LL_I2C_WriteReg(i2c, FLTR, fltr);
114 #endif
115 }
116
117
stm32_i2c_master_finish(const struct device * dev)118 static void stm32_i2c_master_finish(const struct device *dev)
119 {
120 const struct i2c_stm32_config *cfg = dev->config;
121 I2C_TypeDef *i2c = cfg->i2c;
122
123 #ifdef CONFIG_I2C_STM32_INTERRUPT
124 stm32_i2c_disable_transfer_interrupts(dev);
125 #endif
126
127 #if defined(CONFIG_I2C_TARGET)
128 struct i2c_stm32_data *data = dev->data;
129 data->master_active = false;
130 if (!data->slave_attached) {
131 LL_I2C_Disable(i2c);
132 } else {
133 stm32_i2c_enable_transfer_interrupts(dev);
134 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
135 }
136 #else
137 LL_I2C_Disable(i2c);
138 #endif
139 }
140
msg_init(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave,uint32_t transfer)141 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
142 uint8_t *next_msg_flags, uint16_t slave,
143 uint32_t transfer)
144 {
145 const struct i2c_stm32_config *cfg = dev->config;
146 struct i2c_stm32_data *data = dev->data;
147 I2C_TypeDef *i2c = cfg->i2c;
148
149 ARG_UNUSED(next_msg_flags);
150
151 #ifdef CONFIG_I2C_STM32_INTERRUPT
152 k_sem_reset(&data->device_sync_sem);
153 #endif
154
155 data->current.len = msg->len;
156 data->current.buf = msg->buf;
157 data->current.flags = msg->flags;
158 data->current.is_restart = 0U;
159 data->current.is_write = (transfer == I2C_REQUEST_WRITE);
160 data->current.is_arlo = 0U;
161 data->current.is_err = 0U;
162 data->current.is_nack = 0U;
163 data->current.msg = msg;
164 #if defined(CONFIG_I2C_TARGET)
165 data->master_active = true;
166 #endif
167 data->slave_address = slave;
168
169 LL_I2C_Enable(i2c);
170
171 LL_I2C_DisableBitPOS(i2c);
172 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
173 if (msg->flags & I2C_MSG_RESTART) {
174 stm32_i2c_generate_start_condition(i2c);
175 }
176 }
177
msg_end(const struct device * dev,uint8_t * next_msg_flags,const char * funcname)178 static int32_t msg_end(const struct device *dev, uint8_t *next_msg_flags,
179 const char *funcname)
180 {
181 struct i2c_stm32_data *data = dev->data;
182
183 if (data->current.is_nack || data->current.is_err ||
184 data->current.is_arlo) {
185 goto error;
186 }
187
188 if (!next_msg_flags) {
189 stm32_i2c_master_finish(dev);
190 }
191
192 return 0;
193
194 error:
195 if (data->current.is_arlo) {
196 LOG_DBG("%s: ARLO %d", funcname,
197 data->current.is_arlo);
198 data->current.is_arlo = 0U;
199 }
200
201 if (data->current.is_nack) {
202 LOG_DBG("%s: NACK", funcname);
203 data->current.is_nack = 0U;
204 }
205
206 if (data->current.is_err) {
207 LOG_DBG("%s: ERR %d", funcname,
208 data->current.is_err);
209 data->current.is_err = 0U;
210 }
211 stm32_i2c_master_finish(dev);
212
213 return -EIO;
214 }
215
216 #ifdef CONFIG_I2C_STM32_INTERRUPT
217
stm32_i2c_master_mode_end(const struct device * dev)218 static void stm32_i2c_master_mode_end(const struct device *dev)
219 {
220 struct i2c_stm32_data *data = dev->data;
221
222 k_sem_give(&data->device_sync_sem);
223 }
224
handle_sb(const struct device * dev)225 static inline void handle_sb(const struct device *dev)
226 {
227 const struct i2c_stm32_config *cfg = dev->config;
228 struct i2c_stm32_data *data = dev->data;
229 I2C_TypeDef *i2c = cfg->i2c;
230
231 uint16_t saddr = data->slave_address;
232 uint8_t slave;
233
234 if (I2C_ADDR_10_BITS & data->dev_config) {
235 slave = (((saddr & 0x0300) >> 7) & 0xFF);
236 uint8_t header = slave | HEADER;
237
238 if (data->current.is_restart == 0U) {
239 data->current.is_restart = 1U;
240 } else {
241 header |= I2C_REQUEST_READ;
242 data->current.is_restart = 0U;
243 }
244 LL_I2C_TransmitData8(i2c, header);
245
246 return;
247 }
248 slave = (saddr << 1) & 0xFF;
249 if (data->current.is_write) {
250 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
251 } else {
252 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
253 if (data->current.len == 2) {
254 LL_I2C_EnableBitPOS(i2c);
255 }
256 }
257 }
258
handle_addr(const struct device * dev)259 static inline void handle_addr(const struct device *dev)
260 {
261 const struct i2c_stm32_config *cfg = dev->config;
262 struct i2c_stm32_data *data = dev->data;
263 I2C_TypeDef *i2c = cfg->i2c;
264
265 if (I2C_ADDR_10_BITS & data->dev_config) {
266 if (!data->current.is_write && data->current.is_restart) {
267 data->current.is_restart = 0U;
268 LL_I2C_ClearFlag_ADDR(i2c);
269 stm32_i2c_generate_start_condition(i2c);
270
271 return;
272 }
273 }
274
275 if (data->current.is_write) {
276 LL_I2C_ClearFlag_ADDR(i2c);
277 return;
278 }
279 /* according to STM32F1 errata we need to handle these corner cases in
280 * specific way.
281 * Please ref to STM32F10xxC/D/E I2C peripheral Errata sheet 2.14.1
282 */
283 if (data->current.len == 0U && IS_ENABLED(CONFIG_SOC_SERIES_STM32F1X)) {
284 LL_I2C_GenerateStopCondition(i2c);
285 } else if (data->current.len == 1U) {
286 /* Single byte reception: enable NACK and clear POS */
287 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
288 #ifdef CONFIG_SOC_SERIES_STM32F1X
289 LL_I2C_ClearFlag_ADDR(i2c);
290 LL_I2C_GenerateStopCondition(i2c);
291 #endif
292 } else if (data->current.len == 2U) {
293 #ifdef CONFIG_SOC_SERIES_STM32F1X
294 LL_I2C_ClearFlag_ADDR(i2c);
295 #endif
296 /* 2-byte reception: enable NACK and set POS */
297 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
298 LL_I2C_EnableBitPOS(i2c);
299 }
300 LL_I2C_ClearFlag_ADDR(i2c);
301 }
302
handle_txe(const struct device * dev)303 static inline void handle_txe(const struct device *dev)
304 {
305 const struct i2c_stm32_config *cfg = dev->config;
306 struct i2c_stm32_data *data = dev->data;
307 I2C_TypeDef *i2c = cfg->i2c;
308
309 if (data->current.len) {
310 data->current.len--;
311 if (data->current.len == 0U) {
312 /*
313 * This is the last byte to transmit disable Buffer
314 * interrupt and wait for a BTF interrupt
315 */
316 LL_I2C_DisableIT_BUF(i2c);
317 }
318 LL_I2C_TransmitData8(i2c, *data->current.buf);
319 data->current.buf++;
320 } else {
321 if (data->current.flags & I2C_MSG_STOP) {
322 LL_I2C_GenerateStopCondition(i2c);
323 }
324 if (LL_I2C_IsActiveFlag_BTF(i2c)) {
325 /* Read DR to clear BTF flag */
326 LL_I2C_ReceiveData8(i2c);
327 }
328
329 k_sem_give(&data->device_sync_sem);
330 }
331 }
332
handle_rxne(const struct device * dev)333 static inline void handle_rxne(const struct device *dev)
334 {
335 const struct i2c_stm32_config *cfg = dev->config;
336 struct i2c_stm32_data *data = dev->data;
337 I2C_TypeDef *i2c = cfg->i2c;
338
339 if (data->current.len > 0) {
340 switch (data->current.len) {
341 case 1:
342 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
343 LL_I2C_DisableBitPOS(i2c);
344 /* Single byte reception */
345 if (data->current.flags & I2C_MSG_STOP) {
346 LL_I2C_GenerateStopCondition(i2c);
347 }
348 LL_I2C_DisableIT_BUF(i2c);
349 data->current.len--;
350 *data->current.buf = LL_I2C_ReceiveData8(i2c);
351 data->current.buf++;
352
353 k_sem_give(&data->device_sync_sem);
354 break;
355 case 2:
356 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
357 LL_I2C_EnableBitPOS(i2c);
358 __fallthrough;
359 case 3:
360 /*
361 * 2-byte, 3-byte reception and for N-2, N-1,
362 * N when N > 3
363 */
364 LL_I2C_DisableIT_BUF(i2c);
365 break;
366 default:
367 /* N byte reception when N > 3 */
368 data->current.len--;
369 *data->current.buf = LL_I2C_ReceiveData8(i2c);
370 data->current.buf++;
371 }
372 } else {
373
374 if (data->current.flags & I2C_MSG_STOP) {
375 LL_I2C_GenerateStopCondition(i2c);
376 }
377 k_sem_give(&data->device_sync_sem);
378 }
379 }
380
handle_btf(const struct device * dev)381 static inline void handle_btf(const struct device *dev)
382 {
383 const struct i2c_stm32_config *cfg = dev->config;
384 struct i2c_stm32_data *data = dev->data;
385 I2C_TypeDef *i2c = cfg->i2c;
386
387 if (data->current.is_write) {
388 handle_txe(dev);
389 } else {
390 uint32_t counter = 0U;
391
392 switch (data->current.len) {
393 case 2:
394 /*
395 * Stop condition must be generated before reading the
396 * last two bytes.
397 */
398 if (data->current.flags & I2C_MSG_STOP) {
399 LL_I2C_GenerateStopCondition(i2c);
400 }
401
402 for (counter = 2U; counter > 0; counter--) {
403 data->current.len--;
404 *data->current.buf = LL_I2C_ReceiveData8(i2c);
405 data->current.buf++;
406 }
407 k_sem_give(&data->device_sync_sem);
408 break;
409 case 3:
410 /* Set NACK before reading N-2 byte*/
411 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
412 data->current.len--;
413 *data->current.buf = LL_I2C_ReceiveData8(i2c);
414 data->current.buf++;
415 break;
416 default:
417 handle_rxne(dev);
418 }
419 }
420 }
421
422
423 #if defined(CONFIG_I2C_TARGET)
stm32_i2c_slave_event(const struct device * dev)424 static void stm32_i2c_slave_event(const struct device *dev)
425 {
426 const struct i2c_stm32_config *cfg = dev->config;
427 struct i2c_stm32_data *data = dev->data;
428 I2C_TypeDef *i2c = cfg->i2c;
429 const struct i2c_target_callbacks *slave_cb =
430 data->slave_cfg->callbacks;
431
432 if (LL_I2C_IsActiveFlag_TXE(i2c) && LL_I2C_IsActiveFlag_BTF(i2c)) {
433 uint8_t val;
434 slave_cb->read_processed(data->slave_cfg, &val);
435 LL_I2C_TransmitData8(i2c, val);
436 return;
437 }
438
439 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
440 uint8_t val = LL_I2C_ReceiveData8(i2c);
441 if (slave_cb->write_received(data->slave_cfg, val)) {
442 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
443 }
444 return;
445 }
446
447 if (LL_I2C_IsActiveFlag_AF(i2c)) {
448 LL_I2C_ClearFlag_AF(i2c);
449 }
450
451 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
452 LL_I2C_ClearFlag_STOP(i2c);
453 slave_cb->stop(data->slave_cfg);
454 /* Prepare to ACK next transmissions address byte */
455 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
456 }
457
458 if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
459 uint32_t dir = LL_I2C_GetTransferDirection(i2c);
460 if (dir == LL_I2C_DIRECTION_READ) {
461 slave_cb->write_requested(data->slave_cfg);
462 LL_I2C_EnableIT_RX(i2c);
463 } else {
464 uint8_t val;
465 slave_cb->read_requested(data->slave_cfg, &val);
466 LL_I2C_TransmitData8(i2c, val);
467 LL_I2C_EnableIT_TX(i2c);
468 }
469
470 stm32_i2c_enable_transfer_interrupts(dev);
471 }
472 }
473
474 /* Attach and start I2C as slave */
i2c_stm32_target_register(const struct device * dev,struct i2c_target_config * config)475 int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config)
476 {
477 const struct i2c_stm32_config *cfg = dev->config;
478 struct i2c_stm32_data *data = dev->data;
479 I2C_TypeDef *i2c = cfg->i2c;
480 uint32_t bitrate_cfg;
481 int ret;
482
483 if (!config) {
484 return -EINVAL;
485 }
486
487 if (data->slave_attached) {
488 return -EBUSY;
489 }
490
491 if (data->master_active) {
492 return -EBUSY;
493 }
494
495 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
496
497 ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
498 if (ret < 0) {
499 LOG_ERR("i2c: failure initializing");
500 return ret;
501 }
502
503 data->slave_cfg = config;
504
505 LL_I2C_Enable(i2c);
506
507 if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
508 return -ENOTSUP;
509 }
510 LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
511 data->slave_attached = true;
512
513 LOG_DBG("i2c: target registered");
514
515 stm32_i2c_enable_transfer_interrupts(dev);
516 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
517
518 return 0;
519 }
520
i2c_stm32_target_unregister(const struct device * dev,struct i2c_target_config * config)521 int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config)
522 {
523 const struct i2c_stm32_config *cfg = dev->config;
524 struct i2c_stm32_data *data = dev->data;
525 I2C_TypeDef *i2c = cfg->i2c;
526
527 if (!data->slave_attached) {
528 return -EINVAL;
529 }
530
531 if (data->master_active) {
532 return -EBUSY;
533 }
534
535 stm32_i2c_disable_transfer_interrupts(dev);
536
537 LL_I2C_ClearFlag_AF(i2c);
538 LL_I2C_ClearFlag_STOP(i2c);
539 LL_I2C_ClearFlag_ADDR(i2c);
540
541 LL_I2C_Disable(i2c);
542
543 data->slave_attached = false;
544
545 LOG_DBG("i2c: slave unregistered");
546
547 return 0;
548 }
549 #endif /* defined(CONFIG_I2C_TARGET) */
550
stm32_i2c_event_isr(void * arg)551 void stm32_i2c_event_isr(void *arg)
552 {
553 const struct device *dev = (const struct device *)arg;
554 const struct i2c_stm32_config *cfg = dev->config;
555 struct i2c_stm32_data *data = dev->data;
556 I2C_TypeDef *i2c = cfg->i2c;
557
558 #if defined(CONFIG_I2C_TARGET)
559 if (data->slave_attached && !data->master_active) {
560 stm32_i2c_slave_event(dev);
561 return;
562 }
563 #endif
564
565 if (LL_I2C_IsActiveFlag_SB(i2c)) {
566 handle_sb(dev);
567 } else if (LL_I2C_IsActiveFlag_ADD10(i2c)) {
568 LL_I2C_TransmitData8(i2c, data->slave_address);
569 } else if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
570 handle_addr(dev);
571 } else if (LL_I2C_IsActiveFlag_BTF(i2c)) {
572 handle_btf(dev);
573 } else if (LL_I2C_IsActiveFlag_TXE(i2c) && data->current.is_write) {
574 handle_txe(dev);
575 } else if (LL_I2C_IsActiveFlag_RXNE(i2c) && !data->current.is_write) {
576 handle_rxne(dev);
577 }
578 }
579
stm32_i2c_error_isr(void * arg)580 void stm32_i2c_error_isr(void *arg)
581 {
582 const struct device *dev = (const struct device *)arg;
583 const struct i2c_stm32_config *cfg = dev->config;
584 struct i2c_stm32_data *data = dev->data;
585 I2C_TypeDef *i2c = cfg->i2c;
586
587 #if defined(CONFIG_I2C_TARGET)
588 if (data->slave_attached && !data->master_active) {
589 /* No need for a slave error function right now. */
590 return;
591 }
592 #endif
593
594 if (LL_I2C_IsActiveFlag_AF(i2c)) {
595 LL_I2C_ClearFlag_AF(i2c);
596 LL_I2C_GenerateStopCondition(i2c);
597 data->current.is_nack = 1U;
598 goto end;
599 }
600 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
601 LL_I2C_ClearFlag_ARLO(i2c);
602 data->current.is_arlo = 1U;
603 goto end;
604 }
605
606 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
607 LL_I2C_ClearFlag_BERR(i2c);
608 data->current.is_err = 1U;
609 goto end;
610 }
611 return;
612 end:
613 stm32_i2c_master_mode_end(dev);
614 }
615
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)616 static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
617 uint8_t *next_msg_flags, uint16_t saddr)
618 {
619 struct i2c_stm32_data *data = dev->data;
620
621 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
622
623 stm32_i2c_enable_transfer_interrupts(dev);
624
625 if (k_sem_take(&data->device_sync_sem,
626 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
627 LOG_DBG("%s: WRITE timeout", __func__);
628 stm32_i2c_reset(dev);
629 return -EIO;
630 }
631
632 return msg_end(dev, next_msg_flags, __func__);
633 }
634
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)635 static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
636 uint8_t *next_msg_flags, uint16_t saddr)
637 {
638 const struct i2c_stm32_config *cfg = dev->config;
639 struct i2c_stm32_data *data = dev->data;
640 I2C_TypeDef *i2c = cfg->i2c;
641
642 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
643
644 stm32_i2c_enable_transfer_interrupts(dev);
645 LL_I2C_EnableIT_RX(i2c);
646
647 if (k_sem_take(&data->device_sync_sem,
648 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
649 LOG_DBG("%s: READ timeout", __func__);
650 stm32_i2c_reset(dev);
651 return -EIO;
652 }
653
654 return msg_end(dev, next_msg_flags, __func__);
655 }
656
657 #else /* CONFIG_I2C_STM32_INTERRUPT */
658
check_errors(const struct device * dev,const char * funcname)659 static inline int check_errors(const struct device *dev, const char *funcname)
660 {
661 const struct i2c_stm32_config *cfg = dev->config;
662 struct i2c_stm32_data *data = dev->data;
663 I2C_TypeDef *i2c = cfg->i2c;
664
665 if (LL_I2C_IsActiveFlag_AF(i2c)) {
666 LL_I2C_ClearFlag_AF(i2c);
667 LOG_DBG("%s: NACK", funcname);
668 data->current.is_nack = 1U;
669 goto error;
670 }
671
672 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
673 LL_I2C_ClearFlag_ARLO(i2c);
674 LOG_DBG("%s: ARLO", funcname);
675 data->current.is_arlo = 1U;
676 goto error;
677 }
678
679 if (LL_I2C_IsActiveFlag_OVR(i2c)) {
680 LL_I2C_ClearFlag_OVR(i2c);
681 LOG_DBG("%s: OVR", funcname);
682 data->current.is_err = 1U;
683 goto error;
684 }
685
686 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
687 LL_I2C_ClearFlag_BERR(i2c);
688 LOG_DBG("%s: BERR", funcname);
689 data->current.is_err = 1U;
690 goto error;
691 }
692
693 return 0;
694 error:
695 return -EIO;
696 }
697
stm32_i2c_wait_timeout(uint16_t * timeout)698 static int stm32_i2c_wait_timeout(uint16_t *timeout)
699 {
700 if (*timeout == 0) {
701 return 1;
702 } else {
703 k_busy_wait(1);
704 (*timeout)--;
705 return 0;
706 }
707 }
708
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)709 static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
710 uint8_t *next_msg_flags, uint16_t saddr)
711 {
712 const struct i2c_stm32_config *cfg = dev->config;
713 struct i2c_stm32_data *data = dev->data;
714 I2C_TypeDef *i2c = cfg->i2c;
715 uint32_t len = msg->len;
716 uint16_t timeout;
717 uint8_t *buf = msg->buf;
718 int32_t res;
719
720 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
721
722 if (msg->flags & I2C_MSG_RESTART) {
723 timeout = STM32_I2C_TIMEOUT_USEC;
724 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
725 if (stm32_i2c_wait_timeout(&timeout)) {
726 LL_I2C_GenerateStopCondition(i2c);
727 data->current.is_err = 1U;
728 goto end;
729 }
730 }
731
732 if (I2C_ADDR_10_BITS & data->dev_config) {
733 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
734 uint8_t header = slave | HEADER;
735
736 LL_I2C_TransmitData8(i2c, header);
737 timeout = STM32_I2C_TIMEOUT_USEC;
738 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
739 if (stm32_i2c_wait_timeout(&timeout)) {
740 LL_I2C_GenerateStopCondition(i2c);
741 data->current.is_err = 1U;
742 goto end;
743 }
744 }
745
746 slave = data->slave_address & 0xFF;
747 LL_I2C_TransmitData8(i2c, slave);
748 } else {
749 uint8_t slave = (saddr << 1) & 0xFF;
750
751 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
752 }
753
754 timeout = STM32_I2C_TIMEOUT_USEC;
755 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
756 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
757 LL_I2C_ClearFlag_AF(i2c);
758 LL_I2C_GenerateStopCondition(i2c);
759 data->current.is_nack = 1U;
760 goto end;
761 }
762 }
763 LL_I2C_ClearFlag_ADDR(i2c);
764 }
765
766 while (len) {
767 timeout = STM32_I2C_TIMEOUT_USEC;
768 while (1) {
769 if (LL_I2C_IsActiveFlag_TXE(i2c)) {
770 break;
771 }
772 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
773 LL_I2C_ClearFlag_AF(i2c);
774 LL_I2C_GenerateStopCondition(i2c);
775 data->current.is_nack = 1U;
776 goto end;
777 }
778 }
779 LL_I2C_TransmitData8(i2c, *buf);
780 buf++;
781 len--;
782 }
783
784 timeout = STM32_I2C_TIMEOUT_USEC;
785 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
786 if (stm32_i2c_wait_timeout(&timeout)) {
787 LL_I2C_GenerateStopCondition(i2c);
788 data->current.is_err = 1U;
789 goto end;
790 }
791 }
792
793 if (msg->flags & I2C_MSG_STOP) {
794 LL_I2C_GenerateStopCondition(i2c);
795 }
796
797 end:
798 check_errors(dev, __func__);
799 res = msg_end(dev, next_msg_flags, __func__);
800 if (res < 0) {
801 stm32_i2c_reset(dev);
802 }
803
804 return res;
805 }
806
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)807 static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
808 uint8_t *next_msg_flags, uint16_t saddr)
809 {
810 const struct i2c_stm32_config *cfg = dev->config;
811 struct i2c_stm32_data *data = dev->data;
812 I2C_TypeDef *i2c = cfg->i2c;
813 uint32_t len = msg->len;
814 uint16_t timeout;
815 uint8_t *buf = msg->buf;
816 int32_t res;
817
818 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
819
820 if (msg->flags & I2C_MSG_RESTART) {
821 timeout = STM32_I2C_TIMEOUT_USEC;
822 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
823 if (stm32_i2c_wait_timeout(&timeout)) {
824 LL_I2C_GenerateStopCondition(i2c);
825 data->current.is_err = 1U;
826 goto end;
827 }
828 }
829
830 if (I2C_ADDR_10_BITS & data->dev_config) {
831 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
832 uint8_t header = slave | HEADER;
833
834 LL_I2C_TransmitData8(i2c, header);
835 timeout = STM32_I2C_TIMEOUT_USEC;
836 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
837 if (stm32_i2c_wait_timeout(&timeout)) {
838 LL_I2C_GenerateStopCondition(i2c);
839 data->current.is_err = 1U;
840 goto end;
841 }
842 }
843
844 slave = saddr & 0xFF;
845 LL_I2C_TransmitData8(i2c, slave);
846 timeout = STM32_I2C_TIMEOUT_USEC;
847 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
848 if (stm32_i2c_wait_timeout(&timeout)) {
849 LL_I2C_GenerateStopCondition(i2c);
850 data->current.is_err = 1U;
851 goto end;
852 }
853 }
854
855 LL_I2C_ClearFlag_ADDR(i2c);
856 stm32_i2c_generate_start_condition(i2c);
857 timeout = STM32_I2C_TIMEOUT_USEC;
858 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
859 if (stm32_i2c_wait_timeout(&timeout)) {
860 LL_I2C_GenerateStopCondition(i2c);
861 data->current.is_err = 1U;
862 goto end;
863 }
864 }
865
866 header |= I2C_REQUEST_READ;
867 LL_I2C_TransmitData8(i2c, header);
868 } else {
869 uint8_t slave = ((saddr) << 1) & 0xFF;
870
871 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
872 }
873
874 timeout = STM32_I2C_TIMEOUT_USEC;
875 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
876 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
877 LL_I2C_ClearFlag_AF(i2c);
878 LL_I2C_GenerateStopCondition(i2c);
879 data->current.is_nack = 1U;
880 goto end;
881 }
882 }
883 /* ADDR must be cleared before NACK generation. Either in 2 byte reception
884 * byte 1 will be NACK'ed and slave wont sent the last byte
885 */
886 LL_I2C_ClearFlag_ADDR(i2c);
887 if (len == 1U) {
888 /* Single byte reception: enable NACK and set STOP */
889 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
890 } else if (len == 2U) {
891 /* 2-byte reception: enable NACK and set POS */
892 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
893 LL_I2C_EnableBitPOS(i2c);
894 }
895 }
896
897 while (len) {
898 timeout = STM32_I2C_TIMEOUT_USEC;
899 while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
900 if (stm32_i2c_wait_timeout(&timeout)) {
901 LL_I2C_GenerateStopCondition(i2c);
902 data->current.is_err = 1U;
903 goto end;
904 }
905 }
906
907 timeout = STM32_I2C_TIMEOUT_USEC;
908 switch (len) {
909 case 1:
910 if (msg->flags & I2C_MSG_STOP) {
911 LL_I2C_GenerateStopCondition(i2c);
912 }
913 len--;
914 *buf = LL_I2C_ReceiveData8(i2c);
915 buf++;
916 break;
917 case 2:
918 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
919 if (stm32_i2c_wait_timeout(&timeout)) {
920 LL_I2C_GenerateStopCondition(i2c);
921 data->current.is_err = 1U;
922 goto end;
923 }
924 }
925
926 /*
927 * Stop condition must be generated before reading the
928 * last two bytes.
929 */
930 if (msg->flags & I2C_MSG_STOP) {
931 LL_I2C_GenerateStopCondition(i2c);
932 }
933
934 for (uint32_t counter = 2; counter > 0; counter--) {
935 len--;
936 *buf = LL_I2C_ReceiveData8(i2c);
937 buf++;
938 }
939
940 break;
941 case 3:
942 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
943 if (stm32_i2c_wait_timeout(&timeout)) {
944 LL_I2C_GenerateStopCondition(i2c);
945 data->current.is_err = 1U;
946 goto end;
947 }
948 }
949
950 /* Set NACK before reading N-2 byte*/
951 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
952 __fallthrough;
953 default:
954 len--;
955 *buf = LL_I2C_ReceiveData8(i2c);
956 buf++;
957 }
958 }
959 end:
960 check_errors(dev, __func__);
961 res = msg_end(dev, next_msg_flags, __func__);
962 if (res < 0) {
963 stm32_i2c_reset(dev);
964 }
965
966 return res;
967 }
968 #endif /* CONFIG_I2C_STM32_INTERRUPT */
969
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)970 int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
971 {
972 const struct i2c_stm32_config *cfg = dev->config;
973 struct i2c_stm32_data *data = dev->data;
974 I2C_TypeDef *i2c = cfg->i2c;
975
976 switch (I2C_SPEED_GET(data->dev_config)) {
977 case I2C_SPEED_STANDARD:
978 LL_I2C_ConfigSpeed(i2c, clock, 100000, LL_I2C_DUTYCYCLE_2);
979 break;
980 case I2C_SPEED_FAST:
981 LL_I2C_ConfigSpeed(i2c, clock, 400000, LL_I2C_DUTYCYCLE_2);
982 break;
983 default:
984 return -EINVAL;
985 }
986
987 return 0;
988 }
989
stm32_i2c_transaction(const struct device * dev,struct i2c_msg msg,uint8_t * next_msg_flags,uint16_t periph)990 int stm32_i2c_transaction(const struct device *dev,
991 struct i2c_msg msg, uint8_t *next_msg_flags,
992 uint16_t periph)
993 {
994 int ret;
995
996 if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
997 ret = stm32_i2c_msg_write(dev, &msg, next_msg_flags, periph);
998 } else {
999 ret = stm32_i2c_msg_read(dev, &msg, next_msg_flags, periph);
1000 }
1001 return ret;
1002 }
1003
