1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/pm/device.h>
11 #include <zephyr/pm/device_runtime.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/kernel.h>
14 #include <soc.h>
15 #include <stm32_ll_i2c.h>
16 #include <stm32_ll_rcc.h>
17 #include <errno.h>
18 #include <zephyr/drivers/i2c.h>
19 #include <zephyr/drivers/pinctrl.h>
20 #include "i2c_ll_stm32.h"
21
22 #ifdef CONFIG_I2C_STM32_BUS_RECOVERY
23 #include "i2c_bitbang.h"
24 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
25
26 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
27 #include <zephyr/logging/log.h>
28 #include <zephyr/irq.h>
29 LOG_MODULE_REGISTER(i2c_ll_stm32);
30
31 #include "i2c-priv.h"
32
33 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
34 #define DT_DRV_COMPAT st_stm32_i2c_v2
35 #else
36 #define DT_DRV_COMPAT st_stm32_i2c_v1
37 #endif
38
39 /* This symbol takes the value 1 if one of the device instances */
40 /* is configured in dts with a domain clock */
41 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
42 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
43 #else
44 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
45 #endif
46
i2c_stm32_runtime_configure(const struct device * dev,uint32_t config)47 int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
48 {
49 const struct i2c_stm32_config *cfg = dev->config;
50 struct i2c_stm32_data *data = dev->data;
51 I2C_TypeDef *i2c = cfg->i2c;
52 uint32_t clock = 0U;
53 int ret;
54
55 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
56 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
57 (clock_control_subsys_t)&cfg->pclken[1],
58 &clock) < 0) {
59 LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
60 return -EIO;
61 }
62 } else {
63 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
64 (clock_control_subsys_t) &cfg->pclken[0],
65 &clock) < 0) {
66 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
67 return -EIO;
68 }
69 }
70
71 data->dev_config = config;
72
73 k_sem_take(&data->bus_mutex, K_FOREVER);
74
75 #ifdef CONFIG_PM_DEVICE_RUNTIME
76 (void)pm_device_runtime_get(dev);
77 #else
78 pm_device_busy_set(dev);
79 #endif
80
81 LL_I2C_Disable(i2c);
82 LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
83 ret = stm32_i2c_configure_timing(dev, clock);
84
85 #ifdef CONFIG_PM_DEVICE_RUNTIME
86 (void)pm_device_runtime_put(dev);
87 #else
88 pm_device_busy_clear(dev);
89 #endif
90
91 k_sem_give(&data->bus_mutex);
92
93 return ret;
94 }
95
96 #define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
97
i2c_stm32_transfer(const struct device * dev,struct i2c_msg * msg,uint8_t num_msgs,uint16_t slave)98 static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
99 uint8_t num_msgs, uint16_t slave)
100 {
101 struct i2c_stm32_data *data = dev->data;
102 struct i2c_msg *current, *next;
103 int ret = 0;
104
105 /* Check for validity of all messages, to prevent having to abort
106 * in the middle of a transfer
107 */
108 current = msg;
109
110 /*
111 * Set I2C_MSG_RESTART flag on first message in order to send start
112 * condition
113 */
114 current->flags |= I2C_MSG_RESTART;
115
116 for (uint8_t i = 1; i <= num_msgs; i++) {
117
118 if (i < num_msgs) {
119 next = current + 1;
120
121 /*
122 * Restart condition between messages
123 * of different directions is required
124 */
125 if (OPERATION(current) != OPERATION(next)) {
126 if (!(next->flags & I2C_MSG_RESTART)) {
127 ret = -EINVAL;
128 break;
129 }
130 }
131
132 /* Stop condition is only allowed on last message */
133 if (current->flags & I2C_MSG_STOP) {
134 ret = -EINVAL;
135 break;
136 }
137 } else {
138 /* Stop condition is required for the last message */
139 current->flags |= I2C_MSG_STOP;
140 }
141
142 current++;
143 }
144
145 if (ret) {
146 return ret;
147 }
148
149 /* Send out messages */
150 k_sem_take(&data->bus_mutex, K_FOREVER);
151
152 /* Prevent driver from being suspended by PM until I2C transaction is complete */
153 #ifdef CONFIG_PM_DEVICE_RUNTIME
154 (void)pm_device_runtime_get(dev);
155 #else
156 pm_device_busy_set(dev);
157 #endif
158
159 current = msg;
160
161 while (num_msgs > 0) {
162 uint8_t *next_msg_flags = NULL;
163
164 if (num_msgs > 1) {
165 next = current + 1;
166 next_msg_flags = &(next->flags);
167 }
168 ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
169 if (ret < 0) {
170 break;
171 }
172 current++;
173 num_msgs--;
174 }
175
176 #ifdef CONFIG_PM_DEVICE_RUNTIME
177 (void)pm_device_runtime_put(dev);
178 #else
179 pm_device_busy_clear(dev);
180 #endif
181
182 k_sem_give(&data->bus_mutex);
183
184 return ret;
185 }
186
187 #if CONFIG_I2C_STM32_BUS_RECOVERY
i2c_stm32_bitbang_set_scl(void * io_context,int state)188 static void i2c_stm32_bitbang_set_scl(void *io_context, int state)
189 {
190 const struct i2c_stm32_config *config = io_context;
191
192 gpio_pin_set_dt(&config->scl, state);
193 }
194
i2c_stm32_bitbang_set_sda(void * io_context,int state)195 static void i2c_stm32_bitbang_set_sda(void *io_context, int state)
196 {
197 const struct i2c_stm32_config *config = io_context;
198
199 gpio_pin_set_dt(&config->sda, state);
200 }
201
i2c_stm32_bitbang_get_sda(void * io_context)202 static int i2c_stm32_bitbang_get_sda(void *io_context)
203 {
204 const struct i2c_stm32_config *config = io_context;
205
206 return gpio_pin_get_dt(&config->sda) == 0 ? 0 : 1;
207 }
208
i2c_stm32_recover_bus(const struct device * dev)209 static int i2c_stm32_recover_bus(const struct device *dev)
210 {
211 const struct i2c_stm32_config *config = dev->config;
212 struct i2c_stm32_data *data = dev->data;
213 struct i2c_bitbang bitbang_ctx;
214 struct i2c_bitbang_io bitbang_io = {
215 .set_scl = i2c_stm32_bitbang_set_scl,
216 .set_sda = i2c_stm32_bitbang_set_sda,
217 .get_sda = i2c_stm32_bitbang_get_sda,
218 };
219 uint32_t bitrate_cfg;
220 int error = 0;
221
222 LOG_ERR("attempting to recover bus");
223
224 if (!gpio_is_ready_dt(&config->scl)) {
225 LOG_ERR("SCL GPIO device not ready");
226 return -EIO;
227 }
228
229 if (!gpio_is_ready_dt(&config->sda)) {
230 LOG_ERR("SDA GPIO device not ready");
231 return -EIO;
232 }
233
234 k_sem_take(&data->bus_mutex, K_FOREVER);
235
236 error = gpio_pin_configure_dt(&config->scl, GPIO_OUTPUT_HIGH);
237 if (error != 0) {
238 LOG_ERR("failed to configure SCL GPIO (err %d)", error);
239 goto restore;
240 }
241
242 error = gpio_pin_configure_dt(&config->sda, GPIO_OUTPUT_HIGH);
243 if (error != 0) {
244 LOG_ERR("failed to configure SDA GPIO (err %d)", error);
245 goto restore;
246 }
247
248 i2c_bitbang_init(&bitbang_ctx, &bitbang_io, (void *)config);
249
250 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate) | I2C_MODE_CONTROLLER;
251 error = i2c_bitbang_configure(&bitbang_ctx, bitrate_cfg);
252 if (error != 0) {
253 LOG_ERR("failed to configure I2C bitbang (err %d)", error);
254 goto restore;
255 }
256
257 error = i2c_bitbang_recover_bus(&bitbang_ctx);
258 if (error != 0) {
259 LOG_ERR("failed to recover bus (err %d)", error);
260 }
261
262 restore:
263 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
264
265 k_sem_give(&data->bus_mutex);
266
267 return error;
268 }
269 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
270
271
272 static const struct i2c_driver_api api_funcs = {
273 .configure = i2c_stm32_runtime_configure,
274 .transfer = i2c_stm32_transfer,
275 #if CONFIG_I2C_STM32_BUS_RECOVERY
276 .recover_bus = i2c_stm32_recover_bus,
277 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
278 #if defined(CONFIG_I2C_TARGET)
279 .target_register = i2c_stm32_target_register,
280 .target_unregister = i2c_stm32_target_unregister,
281 #endif
282 };
283
284 #ifdef CONFIG_PM_DEVICE
285
i2c_stm32_suspend(const struct device * dev)286 static int i2c_stm32_suspend(const struct device *dev)
287 {
288 int ret;
289 const struct i2c_stm32_config *cfg = dev->config;
290 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
291
292 /* Disable device clock. */
293 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
294 if (ret < 0) {
295 LOG_ERR("failure disabling I2C clock");
296 return ret;
297 }
298
299 /* Move pins to sleep state */
300 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
301 if (ret == -ENOENT) {
302 /* Warn but don't block suspend */
303 LOG_WRN("I2C pinctrl sleep state not available ");
304 } else if (ret < 0) {
305 return ret;
306 }
307
308 return 0;
309 }
310
311 #endif
312
i2c_stm32_activate(const struct device * dev)313 static int i2c_stm32_activate(const struct device *dev)
314 {
315 int ret;
316 const struct i2c_stm32_config *cfg = dev->config;
317 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
318
319 /* Move pins to active/default state */
320 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
321 if (ret < 0) {
322 LOG_ERR("I2C pinctrl setup failed (%d)", ret);
323 return ret;
324 }
325
326 /* Enable device clock. */
327 if (clock_control_on(clk,
328 (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
329 LOG_ERR("i2c: failure enabling clock");
330 return -EIO;
331 }
332
333 return 0;
334 }
335
336
i2c_stm32_init(const struct device * dev)337 static int i2c_stm32_init(const struct device *dev)
338 {
339 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
340 const struct i2c_stm32_config *cfg = dev->config;
341 uint32_t bitrate_cfg;
342 int ret;
343 struct i2c_stm32_data *data = dev->data;
344 #ifdef CONFIG_I2C_STM32_INTERRUPT
345 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
346 cfg->irq_config_func(dev);
347 #endif
348
349 /*
350 * initialize mutex used when multiple transfers
351 * are taking place to guarantee that each one is
352 * atomic and has exclusive access to the I2C bus.
353 */
354 k_sem_init(&data->bus_mutex, 1, 1);
355
356 if (!device_is_ready(clk)) {
357 LOG_ERR("clock control device not ready");
358 return -ENODEV;
359 }
360
361 i2c_stm32_activate(dev);
362
363 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
364 /* Enable I2C clock source */
365 ret = clock_control_configure(clk,
366 (clock_control_subsys_t) &cfg->pclken[1],
367 NULL);
368 if (ret < 0) {
369 return -EIO;
370 }
371 }
372
373 #if defined(CONFIG_SOC_SERIES_STM32F1X)
374 /*
375 * Force i2c reset for STM32F1 series.
376 * So that they can enter master mode properly.
377 * Issue described in ES096 2.14.7
378 */
379 I2C_TypeDef *i2c = cfg->i2c;
380
381 LL_I2C_EnableReset(i2c);
382 LL_I2C_DisableReset(i2c);
383 #endif
384
385 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
386
387 ret = i2c_stm32_runtime_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
388 if (ret < 0) {
389 LOG_ERR("i2c: failure initializing");
390 return ret;
391 }
392
393 #ifdef CONFIG_PM_DEVICE_RUNTIME
394 i2c_stm32_suspend(dev);
395 pm_device_init_suspended(dev);
396 (void)pm_device_runtime_enable(dev);
397 #endif
398
399 return 0;
400 }
401
402 #ifdef CONFIG_PM_DEVICE
403
i2c_stm32_pm_action(const struct device * dev,enum pm_device_action action)404 static int i2c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
405 {
406 int err;
407
408 switch (action) {
409 case PM_DEVICE_ACTION_RESUME:
410 err = i2c_stm32_activate(dev);
411 break;
412 case PM_DEVICE_ACTION_SUSPEND:
413 err = i2c_stm32_suspend(dev);
414 break;
415 default:
416 return -ENOTSUP;
417 }
418
419 return err;
420 }
421
422 #endif
423
424 /* Macros for I2C instance declaration */
425
426 #ifdef CONFIG_I2C_STM32_INTERRUPT
427
428 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
429 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
430 do { \
431 IRQ_CONNECT(DT_INST_IRQN(index), \
432 DT_INST_IRQ(index, priority), \
433 stm32_i2c_combined_isr, \
434 DEVICE_DT_INST_GET(index), 0); \
435 irq_enable(DT_INST_IRQN(index)); \
436 } while (false)
437 #else
438 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
439 do { \
440 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
441 DT_INST_IRQ_BY_NAME(index, event, priority),\
442 stm32_i2c_event_isr, \
443 DEVICE_DT_INST_GET(index), 0); \
444 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
445 \
446 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
447 DT_INST_IRQ_BY_NAME(index, error, priority),\
448 stm32_i2c_error_isr, \
449 DEVICE_DT_INST_GET(index), 0); \
450 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
451 } while (false)
452 #endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
453
454 #define STM32_I2C_IRQ_HANDLER_DECL(index) \
455 static void i2c_stm32_irq_config_func_##index(const struct device *dev)
456 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
457 .irq_config_func = i2c_stm32_irq_config_func_##index,
458 #define STM32_I2C_IRQ_HANDLER(index) \
459 static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
460 { \
461 STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
462 }
463 #else
464
465 #define STM32_I2C_IRQ_HANDLER_DECL(index)
466 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
467 #define STM32_I2C_IRQ_HANDLER(index)
468
469 #endif /* CONFIG_I2C_STM32_INTERRUPT */
470
471 #if CONFIG_I2C_STM32_BUS_RECOVERY
472 #define I2C_STM32_SCL_INIT(n) .scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}),
473 #define I2C_STM32_SDA_INIT(n) .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),
474 #else
475 #define I2C_STM32_SCL_INIT(n)
476 #define I2C_STM32_SDA_INIT(n)
477 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
478
479 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
480 #define DEFINE_TIMINGS(index) \
481 static const uint32_t i2c_timings_##index[] = \
482 DT_INST_PROP_OR(index, timings, {});
483 #define USE_TIMINGS(index) \
484 .timings = (const struct i2c_config_timing *) i2c_timings_##index, \
485 .n_timings = ARRAY_SIZE(i2c_timings_##index),
486 #else /* V2 */
487 #define DEFINE_TIMINGS(index)
488 #define USE_TIMINGS(index)
489 #endif /* V2 */
490
491 #define STM32_I2C_INIT(index) \
492 STM32_I2C_IRQ_HANDLER_DECL(index); \
493 \
494 DEFINE_TIMINGS(index) \
495 \
496 PINCTRL_DT_INST_DEFINE(index); \
497 \
498 static const struct stm32_pclken pclken_##index[] = \
499 STM32_DT_INST_CLOCKS(index); \
500 \
501 static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
502 .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
503 .pclken = pclken_##index, \
504 .pclk_len = DT_INST_NUM_CLOCKS(index), \
505 STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
506 .bitrate = DT_INST_PROP(index, clock_frequency), \
507 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
508 I2C_STM32_SCL_INIT(index) \
509 I2C_STM32_SDA_INIT(index) \
510 USE_TIMINGS(index) \
511 }; \
512 \
513 static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
514 \
515 PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
516 \
517 I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
518 PM_DEVICE_DT_INST_GET(index), \
519 &i2c_stm32_dev_data_##index, \
520 &i2c_stm32_cfg_##index, \
521 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
522 &api_funcs); \
523 \
524 STM32_I2C_IRQ_HANDLER(index)
525
526 DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
527