1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <errno.h>
15 #include <ilm.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
19 #include <zephyr/pm/policy.h>
20 #include <zephyr/sys/util.h>
21
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 /* Start smbus session from idle state */
28 #define I2C_MSG_START BIT(5)
29
30 #define I2C_LINE_SCL_HIGH BIT(0)
31 #define I2C_LINE_SDA_HIGH BIT(1)
32 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
33
34 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
35 #define I2C_FIFO_MODE_MAX_SIZE 32
36 #define I2C_FIFO_MODE_TOTAL_LEN 255
37 #define I2C_MSG_BURST_READ_MASK (I2C_MSG_RESTART | I2C_MSG_STOP | I2C_MSG_READ)
38 #endif
39
40 struct i2c_it8xxx2_config {
41 void (*irq_config_func)(void);
42 uint32_t bitrate;
43 uint8_t *base;
44 uint8_t *reg_mstfctrl;
45 uint8_t i2c_irq_base;
46 uint8_t port;
47 /* SCL GPIO cells */
48 struct gpio_dt_spec scl_gpios;
49 /* SDA GPIO cells */
50 struct gpio_dt_spec sda_gpios;
51 /* I2C alternate configuration */
52 const struct pinctrl_dev_config *pcfg;
53 uint32_t clock_gate_offset;
54 bool fifo_enable;
55 };
56
57 enum i2c_pin_fun {
58 SCL = 0,
59 SDA,
60 };
61
62 enum i2c_ch_status {
63 I2C_CH_NORMAL = 0,
64 I2C_CH_REPEAT_START,
65 I2C_CH_WAIT_READ,
66 I2C_CH_WAIT_NEXT_XFER,
67 };
68
69 struct i2c_it8xxx2_data {
70 enum i2c_ch_status i2ccs;
71 struct i2c_msg *active_msg;
72 struct k_mutex mutex;
73 struct k_sem device_sync_sem;
74 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
75 struct i2c_msg *msgs_list;
76 /* Read or write byte counts. */
77 uint32_t bytecnt;
78 /* Number of messages. */
79 uint8_t num_msgs;
80 uint8_t active_msg_index;
81 #endif
82 /* Index into output data */
83 size_t widx;
84 /* Index into input data */
85 size_t ridx;
86 /* operation freq of i2c */
87 uint32_t bus_freq;
88 /* Error code, if any */
89 uint32_t err;
90 /* address of device */
91 uint16_t addr_16bit;
92 /* Frequency setting */
93 uint8_t freq;
94 /* wait for stop bit interrupt */
95 uint8_t stop;
96 };
97
98 enum i2c_host_status {
99 /* Host busy */
100 HOSTA_HOBY = 0x01,
101 /* Finish Interrupt */
102 HOSTA_FINTR = 0x02,
103 /* Device error */
104 HOSTA_DVER = 0x04,
105 /* Bus error */
106 HOSTA_BSER = 0x08,
107 /* Fail */
108 HOSTA_FAIL = 0x10,
109 /* Not response ACK */
110 HOSTA_NACK = 0x20,
111 /* Time-out error */
112 HOSTA_TMOE = 0x40,
113 /* Byte done status */
114 HOSTA_BDS = 0x80,
115 /* Error bit is set */
116 HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL |
117 HOSTA_NACK | HOSTA_TMOE),
118 /* W/C for next byte */
119 HOSTA_NEXT_BYTE = HOSTA_BDS,
120 /* W/C host status register */
121 HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
122 };
123
124 enum i2c_reset_cause {
125 I2C_RC_NO_IDLE_FOR_START = 1,
126 I2C_RC_TIMEOUT,
127 };
128
i2c_parsing_return_value(const struct device * dev)129 static int i2c_parsing_return_value(const struct device *dev)
130 {
131 const struct i2c_it8xxx2_config *config = dev->config;
132 struct i2c_it8xxx2_data *data = dev->data;
133
134 if (!data->err) {
135 return 0;
136 }
137
138 if (data->err == ETIMEDOUT) {
139 /* Connection timed out */
140 LOG_ERR("I2C ch%d Address:0x%X Transaction time out.",
141 config->port, data->addr_16bit);
142 } else {
143 LOG_DBG("I2C ch%d Address:0x%X Host error bits message:",
144 config->port, data->addr_16bit);
145 /* Host error bits message*/
146 if (data->err & HOSTA_TMOE) {
147 LOG_ERR("Time-out error: hardware time-out error.");
148 }
149 if (data->err & HOSTA_NACK) {
150 LOG_DBG("NACK error: device does not response ACK.");
151 }
152 if (data->err & HOSTA_FAIL) {
153 LOG_ERR("Fail: a processing transmission is killed.");
154 }
155 if (data->err & HOSTA_BSER) {
156 LOG_ERR("BUS error: SMBus has lost arbitration.");
157 }
158 }
159
160 return -EIO;
161 }
162
i2c_get_line_levels(const struct device * dev)163 static int i2c_get_line_levels(const struct device *dev)
164 {
165 const struct i2c_it8xxx2_config *config = dev->config;
166 uint8_t *base = config->base;
167
168 return (IT8XXX2_SMB_SMBPCTL(base) &
169 (IT8XXX2_SMB_SMBDCS | IT8XXX2_SMB_SMBCS));
170 }
171
i2c_is_busy(const struct device * dev)172 static int i2c_is_busy(const struct device *dev)
173 {
174 const struct i2c_it8xxx2_config *config = dev->config;
175 uint8_t *base = config->base;
176
177 return (IT8XXX2_SMB_HOSTA(base) &
178 (HOSTA_HOBY | HOSTA_ALL_WC_BIT));
179 }
180
i2c_bus_not_available(const struct device * dev)181 static int i2c_bus_not_available(const struct device *dev)
182 {
183 if (i2c_is_busy(dev) ||
184 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
185 return -EIO;
186 }
187
188 return 0;
189 }
190
i2c_reset(const struct device * dev)191 static void i2c_reset(const struct device *dev)
192 {
193 const struct i2c_it8xxx2_config *config = dev->config;
194 uint8_t *base = config->base;
195
196 /* bit1, kill current transaction. */
197 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL;
198 IT8XXX2_SMB_HOCTL(base) = 0;
199 /* W/C host status register */
200 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
201 }
202
203 /*
204 * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
205 * (offset 0h ~ 7h).
206 */
i2c_standard_port_timing_regs_400khz(uint8_t port)207 static void i2c_standard_port_timing_regs_400khz(uint8_t port)
208 {
209 /* Port clock frequency depends on setting of timing registers. */
210 IT8XXX2_SMB_SCLKTS(port) = 0;
211 /* Suggested setting of timing registers of 400kHz. */
212 IT8XXX2_SMB_4P7USL = 0x3;
213 IT8XXX2_SMB_4P0USL = 0;
214 IT8XXX2_SMB_300NS = 0x1;
215 IT8XXX2_SMB_250NS = 0x5;
216 IT8XXX2_SMB_45P3USL = 0x6a;
217 IT8XXX2_SMB_45P3USH = 0x1;
218 IT8XXX2_SMB_4P7A4P0H = 0;
219 }
220
221 /* Set clock frequency for i2c port A, B , or C */
i2c_standard_port_set_frequency(const struct device * dev,int freq_hz,int freq_set)222 static void i2c_standard_port_set_frequency(const struct device *dev,
223 int freq_hz, int freq_set)
224 {
225 const struct i2c_it8xxx2_config *config = dev->config;
226
227 /*
228 * If port's clock frequency is 400kHz, we use timing registers
229 * for setting. So we can adjust tlow to meet timing.
230 * The others use basic 50/100/1000 KHz setting.
231 */
232 if (freq_hz == I2C_BITRATE_FAST) {
233 i2c_standard_port_timing_regs_400khz(config->port);
234 } else {
235 IT8XXX2_SMB_SCLKTS(config->port) = freq_set;
236 }
237
238 /* This field defines the SMCLK0/1/2 clock/data low timeout. */
239 IT8XXX2_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
240 }
241
i2c_it8xxx2_configure(const struct device * dev,uint32_t dev_config_raw)242 static int i2c_it8xxx2_configure(const struct device *dev,
243 uint32_t dev_config_raw)
244 {
245 const struct i2c_it8xxx2_config *config = dev->config;
246 struct i2c_it8xxx2_data *const data = dev->data;
247 uint32_t freq_set;
248
249 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
250 return -EINVAL;
251 }
252
253 if (I2C_ADDR_10_BITS & dev_config_raw) {
254 return -EINVAL;
255 }
256
257 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
258
259 switch (data->bus_freq) {
260 case I2C_SPEED_DT:
261 freq_set = IT8XXX2_SMB_SMCLKS_50K;
262 break;
263 case I2C_SPEED_STANDARD:
264 freq_set = IT8XXX2_SMB_SMCLKS_100K;
265 break;
266 case I2C_SPEED_FAST:
267 freq_set = IT8XXX2_SMB_SMCLKS_400K;
268 break;
269 case I2C_SPEED_FAST_PLUS:
270 freq_set = IT8XXX2_SMB_SMCLKS_1M;
271 break;
272 default:
273 return -EINVAL;
274 }
275
276 i2c_standard_port_set_frequency(dev, config->bitrate, freq_set);
277
278 return 0;
279 }
280
i2c_it8xxx2_get_config(const struct device * dev,uint32_t * dev_config)281 static int i2c_it8xxx2_get_config(const struct device *dev,
282 uint32_t *dev_config)
283 {
284 struct i2c_it8xxx2_data *const data = dev->data;
285 uint32_t speed;
286
287 if (!data->bus_freq) {
288 LOG_ERR("The bus frequency is not initially configured.");
289 return -EIO;
290 }
291
292 switch (data->bus_freq) {
293 case I2C_SPEED_DT:
294 case I2C_SPEED_STANDARD:
295 case I2C_SPEED_FAST:
296 case I2C_SPEED_FAST_PLUS:
297 speed = I2C_SPEED_SET(data->bus_freq);
298 break;
299 default:
300 return -ERANGE;
301 }
302
303 *dev_config = (I2C_MODE_CONTROLLER | speed);
304
305 return 0;
306 }
307
i2c_r_last_byte(const struct device * dev)308 void __soc_ram_code i2c_r_last_byte(const struct device *dev)
309 {
310 struct i2c_it8xxx2_data *data = dev->data;
311 const struct i2c_it8xxx2_config *config = dev->config;
312 uint8_t *base = config->base;
313
314 /*
315 * bit5, The firmware shall write 1 to this bit
316 * when the next byte will be the last byte for i2c read.
317 */
318 if ((data->active_msg->flags & I2C_MSG_STOP) &&
319 (data->ridx == data->active_msg->len - 1)) {
320 IT8XXX2_SMB_HOCTL(base) |= IT8XXX2_SMB_LABY;
321 }
322 }
323
i2c_w2r_change_direction(const struct device * dev)324 void __soc_ram_code i2c_w2r_change_direction(const struct device *dev)
325 {
326 const struct i2c_it8xxx2_config *config = dev->config;
327 uint8_t *base = config->base;
328
329 /* I2C switch direction */
330 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
331 i2c_r_last_byte(dev);
332 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
333 } else {
334 /*
335 * bit2, I2C switch direction wait.
336 * bit3, I2C switch direction enable.
337 */
338 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
339 IT8XXX2_SMB_I2C_SW_WAIT;
340 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
341 i2c_r_last_byte(dev);
342 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
343 }
344 }
345
346 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
i2c_fifo_en_w2r(const struct device * dev,bool enable)347 void __soc_ram_code i2c_fifo_en_w2r(const struct device *dev, bool enable)
348 {
349 const struct i2c_it8xxx2_config *config = dev->config;
350 unsigned int key = irq_lock();
351
352 if (enable) {
353 if (config->port == SMB_CHANNEL_A) {
354 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MAIF |
355 IT8XXX2_SMB_MAIFI;
356 } else if (config->port == SMB_CHANNEL_B) {
357 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
358 IT8XXX2_SMB_MBIFI;
359 } else if (config->port == SMB_CHANNEL_C) {
360 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
361 IT8XXX2_SMB_MCIFI;
362 }
363 } else {
364 if (config->port == SMB_CHANNEL_A) {
365 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MAIF |
366 IT8XXX2_SMB_MAIFI);
367 } else if (config->port == SMB_CHANNEL_B) {
368 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
369 IT8XXX2_SMB_MBIFI);
370 } else if (config->port == SMB_CHANNEL_C) {
371 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
372 IT8XXX2_SMB_MCIFI);
373 }
374 }
375
376 irq_unlock(key);
377 }
378
i2c_tran_fifo_write_start(const struct device * dev)379 void __soc_ram_code i2c_tran_fifo_write_start(const struct device *dev)
380 {
381 struct i2c_it8xxx2_data *data = dev->data;
382 const struct i2c_it8xxx2_config *config = dev->config;
383 uint32_t i;
384 uint8_t *base = config->base;
385 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
386
387 /* Clear start flag. */
388 data->active_msg->flags &= ~I2C_MSG_START;
389 /* Enable SMB channel in FIFO mode. */
390 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
391 /* I2C enable. */
392 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
393 IT8XXX2_SMB_I2C_EN |
394 IT8XXX2_SMB_SMHEN;
395 /* Set write byte counts. */
396 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
397 /*
398 * bit[7:1]: Address of the target.
399 * bit[0]: Direction of the host transfer.
400 */
401 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
402 /* The maximum fifo size is 32 bytes. */
403 data->bytecnt = MIN(data->active_msg->len, I2C_FIFO_MODE_MAX_SIZE);
404
405 for (i = 0; i < data->bytecnt; i++) {
406 /* Set host block data byte. */
407 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
408 }
409 /* Calculate the remaining byte counts. */
410 data->bytecnt = data->active_msg->len - data->bytecnt;
411 /*
412 * bit[6] = 1b: Start.
413 * bit[4:2] = 111b: Extend command.
414 * bit[0] = 1b: Host interrupt enable.
415 */
416 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
417 IT8XXX2_SMB_SMCD_EXTND |
418 IT8XXX2_SMB_INTREN;
419 }
420
i2c_tran_fifo_write_next_block(const struct device * dev)421 void __soc_ram_code i2c_tran_fifo_write_next_block(const struct device *dev)
422 {
423 struct i2c_it8xxx2_data *data = dev->data;
424 const struct i2c_it8xxx2_config *config = dev->config;
425 uint32_t i, _bytecnt;
426 uint8_t *base = config->base;
427 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
428
429 /* The maximum fifo size is 32 bytes. */
430 _bytecnt = MIN(data->bytecnt, I2C_FIFO_MODE_MAX_SIZE);
431
432 for (i = 0; i < _bytecnt; i++) {
433 /* Set host block data byte. */
434 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
435 }
436 /* Clear FIFO block done status. */
437 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
438 /* Calculate the remaining byte counts. */
439 data->bytecnt -= _bytecnt;
440 }
441
i2c_tran_fifo_write_finish(const struct device * dev)442 void __soc_ram_code i2c_tran_fifo_write_finish(const struct device *dev)
443 {
444 const struct i2c_it8xxx2_config *config = dev->config;
445 uint8_t *base = config->base;
446
447 /* Clear byte count register. */
448 IT8XXX2_SMB_D0REG(base) = 0;
449 /* W/C */
450 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
451 /* Disable the SMBus host interface. */
452 IT8XXX2_SMB_HOCTL2(base) = 0x00;
453 }
454
i2c_tran_fifo_w2r_change_direction(const struct device * dev)455 int __soc_ram_code i2c_tran_fifo_w2r_change_direction(const struct device *dev)
456 {
457 struct i2c_it8xxx2_data *data = dev->data;
458 const struct i2c_it8xxx2_config *config = dev->config;
459 uint8_t *base = config->base;
460
461 if (++data->active_msg_index >= data->num_msgs) {
462 LOG_ERR("Current message index is error.");
463 data->err = EINVAL;
464 /* W/C */
465 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
466 /* Disable the SMBus host interface. */
467 IT8XXX2_SMB_HOCTL2(base) = 0x00;
468
469 return 0;
470 }
471 /* Set I2C_SW_EN = 1 */
472 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
473 IT8XXX2_SMB_I2C_SW_WAIT;
474 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
475 /* Point to the next msg for the read location. */
476 data->active_msg = &data->msgs_list[data->active_msg_index];
477 /* Set read byte counts. */
478 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
479 data->bytecnt = data->active_msg->len;
480 /* W/C I2C W2R FIFO interrupt status. */
481 IT8XXX2_SMB_IWRFISTA = BIT(config->port);
482
483 return 1;
484 }
485
i2c_tran_fifo_read_start(const struct device * dev)486 void __soc_ram_code i2c_tran_fifo_read_start(const struct device *dev)
487 {
488 struct i2c_it8xxx2_data *data = dev->data;
489 const struct i2c_it8xxx2_config *config = dev->config;
490 uint8_t *base = config->base;
491 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
492
493 /* Clear start flag. */
494 data->active_msg->flags &= ~I2C_MSG_START;
495 /* Enable SMB channel in FIFO mode. */
496 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
497 /* I2C enable. */
498 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
499 IT8XXX2_SMB_I2C_EN |
500 IT8XXX2_SMB_SMHEN;
501 /* Set read byte counts. */
502 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
503 /*
504 * bit[7:1]: Address of the target.
505 * bit[0]: Direction of the host transfer.
506 */
507 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
508 IT8XXX2_SMB_DIR;
509
510 data->bytecnt = data->active_msg->len;
511 /*
512 * bit[6] = 1b: Start.
513 * bit[4:2] = 111b: Extend command.
514 * bit[0] = 1b: Host interrupt enable.
515 */
516 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
517 IT8XXX2_SMB_SMCD_EXTND |
518 IT8XXX2_SMB_INTREN;
519 }
520
i2c_tran_fifo_read_next_block(const struct device * dev)521 void __soc_ram_code i2c_tran_fifo_read_next_block(const struct device *dev)
522 {
523 struct i2c_it8xxx2_data *data = dev->data;
524 const struct i2c_it8xxx2_config *config = dev->config;
525 uint32_t i;
526 uint8_t *base = config->base;
527 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
528
529 for (i = 0; i < I2C_FIFO_MODE_MAX_SIZE; i++) {
530 /* To get received data. */
531 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
532 }
533 /* Clear FIFO block done status. */
534 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
535 /* Calculate the remaining byte counts. */
536 data->bytecnt -= I2C_FIFO_MODE_MAX_SIZE;
537 }
538
i2c_tran_fifo_read_finish(const struct device * dev)539 void __soc_ram_code i2c_tran_fifo_read_finish(const struct device *dev)
540 {
541 struct i2c_it8xxx2_data *data = dev->data;
542 const struct i2c_it8xxx2_config *config = dev->config;
543 uint32_t i;
544 uint8_t *base = config->base;
545
546 for (i = 0; i < data->bytecnt; i++) {
547 /* To get received data. */
548 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
549 }
550 /* Clear byte count register. */
551 IT8XXX2_SMB_D0REG(base) = 0;
552 /* W/C */
553 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
554 /* Disable the SMBus host interface. */
555 IT8XXX2_SMB_HOCTL2(base) = 0x00;
556
557 }
558
i2c_tran_fifo_write_to_read(const struct device * dev)559 int __soc_ram_code i2c_tran_fifo_write_to_read(const struct device *dev)
560 {
561 struct i2c_it8xxx2_data *data = dev->data;
562 const struct i2c_it8xxx2_config *config = dev->config;
563 uint8_t *base = config->base;
564 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
565 int ret = 1;
566
567 if (data->active_msg->flags & I2C_MSG_START) {
568 /* Enable I2C write to read FIFO mode. */
569 i2c_fifo_en_w2r(dev, 1);
570 i2c_tran_fifo_write_start(dev);
571 } else {
572 /* Check block done status. */
573 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
574 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
575 i2c_tran_fifo_read_next_block(dev);
576 } else {
577 i2c_tran_fifo_write_next_block(dev);
578 }
579 } else if (IT8XXX2_SMB_IWRFISTA & BIT(config->port)) {
580 /*
581 * This function returns 0 on a failure to indicate
582 * that the current transaction is completed and
583 * returned the data->err.
584 */
585 ret = i2c_tran_fifo_w2r_change_direction(dev);
586 } else {
587 /* Wait finish. */
588 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
589 i2c_tran_fifo_read_finish(dev);
590 /* Done doing work. */
591 ret = 0;
592 }
593 }
594 }
595
596 return ret;
597 }
598
i2c_tran_fifo_read(const struct device * dev)599 int __soc_ram_code i2c_tran_fifo_read(const struct device *dev)
600 {
601 struct i2c_it8xxx2_data *data = dev->data;
602 const struct i2c_it8xxx2_config *config = dev->config;
603 uint8_t *base = config->base;
604 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
605
606 if (data->active_msg->flags & I2C_MSG_START) {
607 i2c_tran_fifo_read_start(dev);
608 } else {
609 /* Check block done status. */
610 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
611 i2c_tran_fifo_read_next_block(dev);
612 } else {
613 /* Wait finish. */
614 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
615 i2c_tran_fifo_read_finish(dev);
616 /* Done doing work. */
617 return 0;
618 }
619 }
620 }
621
622 return 1;
623 }
624
i2c_tran_fifo_write(const struct device * dev)625 int __soc_ram_code i2c_tran_fifo_write(const struct device *dev)
626 {
627 struct i2c_it8xxx2_data *data = dev->data;
628 const struct i2c_it8xxx2_config *config = dev->config;
629 uint8_t *base = config->base;
630 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
631
632 if (data->active_msg->flags & I2C_MSG_START) {
633 i2c_tran_fifo_write_start(dev);
634 } else {
635 /* Check block done status. */
636 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
637 i2c_tran_fifo_write_next_block(dev);
638 } else {
639 /* Wait finish. */
640 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
641 i2c_tran_fifo_write_finish(dev);
642 /* Done doing work. */
643 return 0;
644 }
645 }
646 }
647
648 return 1;
649 }
650
i2c_fifo_transaction(const struct device * dev)651 int __soc_ram_code i2c_fifo_transaction(const struct device *dev)
652 {
653 struct i2c_it8xxx2_data *data = dev->data;
654 const struct i2c_it8xxx2_config *config = dev->config;
655 uint8_t *base = config->base;
656
657 /* Any error. */
658 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
659 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
660 } else {
661 if (data->num_msgs == 2) {
662 return i2c_tran_fifo_write_to_read(dev);
663 } else if (data->active_msg->flags & I2C_MSG_READ) {
664 return i2c_tran_fifo_read(dev);
665 } else {
666 return i2c_tran_fifo_write(dev);
667 }
668 }
669 /* W/C */
670 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
671 /* Disable the SMBus host interface. */
672 IT8XXX2_SMB_HOCTL2(base) = 0x00;
673
674 return 0;
675 }
676
fifo_mode_allowed(const struct device * dev,struct i2c_msg * msgs)677 bool __soc_ram_code fifo_mode_allowed(const struct device *dev,
678 struct i2c_msg *msgs)
679 {
680 struct i2c_it8xxx2_data *data = dev->data;
681 const struct i2c_it8xxx2_config *config = dev->config;
682
683 /*
684 * If the transaction of write or read is divided into two
685 * transfers(not two messages), the FIFO mode does not support.
686 */
687 if (data->i2ccs != I2C_CH_NORMAL) {
688 return false;
689 }
690 /*
691 * FIFO2 only supports one channel of B or C. If the FIFO of
692 * channel is not enabled, it will select PIO mode.
693 */
694 if (!config->fifo_enable) {
695 return false;
696 }
697 /*
698 * When there is only one message, use the FIFO mode transfer
699 * directly.
700 * Transfer payload too long (>255 bytes), use PIO mode.
701 * Write or read of I2C target address without data, used by
702 * cmd_i2c_scan. Use PIO mode.
703 */
704 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP) &&
705 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN) && (msgs[0].len != 0)) {
706 return true;
707 }
708 /*
709 * When there are two messages, we need to judge whether or not there
710 * is I2C_MSG_RESTART flag from the second message, and then decide to
711 * do the FIFO mode or PIO mode transfer.
712 */
713 if (data->num_msgs == 2) {
714 /*
715 * The first of two messages must be write.
716 * Transfer payload too long (>255 bytes), use PIO mode.
717 */
718 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
719 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
720 /*
721 * The transfer is i2c_burst_read().
722 *
723 * e.g. msg[0].flags = I2C_MSG_WRITE;
724 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
725 * I2C_MSG_STOP;
726 */
727 if ((msgs[1].flags == I2C_MSG_BURST_READ_MASK) &&
728 (msgs[1].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
729 return true;
730 }
731 }
732 }
733
734 return false;
735 }
736 #endif
737
i2c_tran_read(const struct device * dev)738 int __soc_ram_code i2c_tran_read(const struct device *dev)
739 {
740 struct i2c_it8xxx2_data *data = dev->data;
741 const struct i2c_it8xxx2_config *config = dev->config;
742 uint8_t *base = config->base;
743
744 if (data->active_msg->flags & I2C_MSG_START) {
745 /* i2c enable */
746 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
747 IT8XXX2_SMB_I2C_EN |
748 IT8XXX2_SMB_SMHEN;
749 /*
750 * bit0, Direction of the host transfer.
751 * bit[1:7}, Address of the targeted slave.
752 */
753 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
754 IT8XXX2_SMB_DIR;
755 /* clear start flag */
756 data->active_msg->flags &= ~I2C_MSG_START;
757 /*
758 * bit0, Host interrupt enable.
759 * bit[2:4}, Extend command.
760 * bit5, The firmware shall write 1 to this bit
761 * when the next byte will be the last byte.
762 * bit6, start.
763 */
764 if ((data->active_msg->len == 1) &&
765 (data->active_msg->flags & I2C_MSG_STOP)) {
766 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
767 IT8XXX2_SMB_LABY |
768 IT8XXX2_SMB_SMCD_EXTND |
769 IT8XXX2_SMB_INTREN;
770 } else {
771 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
772 IT8XXX2_SMB_SMCD_EXTND |
773 IT8XXX2_SMB_INTREN;
774 }
775 } else {
776 if ((data->i2ccs == I2C_CH_REPEAT_START) ||
777 (data->i2ccs == I2C_CH_WAIT_READ)) {
778 if (data->i2ccs == I2C_CH_REPEAT_START) {
779 /* write to read */
780 i2c_w2r_change_direction(dev);
781 } else {
782 /* For last byte */
783 i2c_r_last_byte(dev);
784 /* W/C for next byte */
785 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
786 }
787 data->i2ccs = I2C_CH_NORMAL;
788 } else if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
789 if (data->ridx < data->active_msg->len) {
790 /* To get received data. */
791 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
792 data->ridx++;
793 /* For last byte */
794 i2c_r_last_byte(dev);
795 /* done */
796 if (data->ridx == data->active_msg->len) {
797 data->active_msg->len = 0;
798 if (data->active_msg->flags & I2C_MSG_STOP) {
799 /* W/C for finish */
800 IT8XXX2_SMB_HOSTA(base) =
801 HOSTA_NEXT_BYTE;
802
803 data->stop = 1;
804 } else {
805 data->i2ccs = I2C_CH_WAIT_READ;
806 return 0;
807 }
808 } else {
809 /* W/C for next byte */
810 IT8XXX2_SMB_HOSTA(base) =
811 HOSTA_NEXT_BYTE;
812 }
813 }
814 }
815 }
816 return 1;
817
818 }
819
i2c_tran_write(const struct device * dev)820 int __soc_ram_code i2c_tran_write(const struct device *dev)
821 {
822 struct i2c_it8xxx2_data *data = dev->data;
823 const struct i2c_it8xxx2_config *config = dev->config;
824 uint8_t *base = config->base;
825
826 if (data->active_msg->flags & I2C_MSG_START) {
827 /* i2c enable */
828 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
829 IT8XXX2_SMB_I2C_EN |
830 IT8XXX2_SMB_SMHEN;
831 /*
832 * bit0, Direction of the host transfer.
833 * bit[1:7}, Address of the targeted slave.
834 */
835 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
836 /* Send first byte */
837 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
838
839 data->widx++;
840 /* clear start flag */
841 data->active_msg->flags &= ~I2C_MSG_START;
842 /*
843 * bit0, Host interrupt enable.
844 * bit[2:4}, Extend command.
845 * bit6, start.
846 */
847 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
848 IT8XXX2_SMB_SMCD_EXTND |
849 IT8XXX2_SMB_INTREN;
850 } else {
851 /* Host has completed the transmission of a byte */
852 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
853 if (data->widx < data->active_msg->len) {
854 /* Send next byte */
855 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
856
857 data->widx++;
858 /* W/C byte done for next byte */
859 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
860
861 if (data->i2ccs == I2C_CH_REPEAT_START) {
862 data->i2ccs = I2C_CH_NORMAL;
863 }
864 } else {
865 /* done */
866 data->active_msg->len = 0;
867 if (data->active_msg->flags & I2C_MSG_STOP) {
868 /* set I2C_EN = 0 */
869 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
870 IT8XXX2_SMB_SMHEN;
871 /* W/C byte done for finish */
872 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
873
874 data->stop = 1;
875 } else {
876 data->i2ccs = I2C_CH_REPEAT_START;
877 return 0;
878 }
879 }
880 }
881 }
882 return 1;
883
884 }
885
i2c_pio_transaction(const struct device * dev)886 int __soc_ram_code i2c_pio_transaction(const struct device *dev)
887 {
888 struct i2c_it8xxx2_data *data = dev->data;
889 const struct i2c_it8xxx2_config *config = dev->config;
890 uint8_t *base = config->base;
891
892 /* any error */
893 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
894 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
895 } else {
896 if (!data->stop) {
897 /*
898 * The return value indicates if there is more data
899 * to be read or written. If the return value = 1,
900 * it means that the interrupt cannot be disable and
901 * continue to transmit data.
902 */
903 if (data->active_msg->flags & I2C_MSG_READ) {
904 return i2c_tran_read(dev);
905 } else {
906 return i2c_tran_write(dev);
907 }
908 }
909 /* wait finish */
910 if (!(IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
911 return 1;
912 }
913 }
914 /* W/C */
915 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
916 /* disable the SMBus host interface */
917 IT8XXX2_SMB_HOCTL2(base) = 0x00;
918
919 data->stop = 0;
920 /* done doing work */
921 return 0;
922 }
923
i2c_it8xxx2_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)924 static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
925 uint8_t num_msgs, uint16_t addr)
926 {
927 struct i2c_it8xxx2_data *data = dev->data;
928 const struct i2c_it8xxx2_config *config = dev->config;
929 int res, ret;
930
931 /* Lock mutex of i2c controller */
932 k_mutex_lock(&data->mutex, K_FOREVER);
933 /*
934 * If the transaction of write to read is divided into two
935 * transfers, the repeat start transfer uses this flag to
936 * exclude checking bus busy.
937 */
938 if (data->i2ccs == I2C_CH_NORMAL) {
939 struct i2c_msg *start_msg = &msgs[0];
940
941 /* Make sure we're in a good state to start */
942 if (i2c_bus_not_available(dev)) {
943 /* Recovery I2C bus */
944 i2c_recover_bus(dev);
945 /*
946 * After resetting I2C bus, if I2C bus is not available
947 * (No external pull-up), drop the transaction.
948 */
949 if (i2c_bus_not_available(dev)) {
950 /* Unlock mutex of i2c controller */
951 k_mutex_unlock(&data->mutex);
952 return -EIO;
953 }
954 }
955
956 start_msg->flags |= I2C_MSG_START;
957 }
958 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
959 /* Store num_msgs to data struct. */
960 data->num_msgs = num_msgs;
961 /* Store msgs to data struct. */
962 data->msgs_list = msgs;
963 bool fifo_mode_enable = fifo_mode_allowed(dev, msgs);
964
965 if (fifo_mode_enable) {
966 /* Block to enter power policy. */
967 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
968 }
969 #endif
970 for (int i = 0; i < num_msgs; i++) {
971
972 data->widx = 0;
973 data->ridx = 0;
974 data->err = 0;
975 data->active_msg = &msgs[i];
976 data->addr_16bit = addr;
977
978 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
979 data->active_msg_index = 0;
980 /*
981 * Start transaction.
982 * The return value indicates if the initial configuration
983 * of I2C transaction for read or write has been completed.
984 */
985 if (fifo_mode_enable) {
986 if (i2c_fifo_transaction(dev)) {
987 /* Enable i2c interrupt */
988 irq_enable(config->i2c_irq_base);
989 }
990 } else
991 #endif
992 {
993 if (i2c_pio_transaction(dev)) {
994 /* Enable i2c interrupt */
995 irq_enable(config->i2c_irq_base);
996 }
997 }
998 /* Wait for the transfer to complete */
999 /* TODO: the timeout should be adjustable */
1000 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
1001 /*
1002 * The irq will be enabled at the condition of start or
1003 * repeat start of I2C. If timeout occurs without being
1004 * wake up during suspend(ex: interrupt is not fired),
1005 * the irq should be disabled immediately.
1006 */
1007 irq_disable(config->i2c_irq_base);
1008 /*
1009 * The transaction is dropped on any error(timeout, NACK, fail,
1010 * bus error, device error).
1011 */
1012 if (data->err) {
1013 break;
1014 }
1015
1016 if (res != 0) {
1017 data->err = ETIMEDOUT;
1018 /* reset i2c port */
1019 i2c_reset(dev);
1020 LOG_ERR("I2C ch%d:0x%X reset cause %d",
1021 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
1022 /* If this message is sent fail, drop the transaction. */
1023 break;
1024 }
1025
1026 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1027 /*
1028 * In FIFO mode, messages are compressed into a single
1029 * transaction.
1030 */
1031 if (fifo_mode_enable) {
1032 break;
1033 }
1034 #endif
1035 }
1036 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1037 if (fifo_mode_enable) {
1038 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1039
1040 /* Disable SMB channels in FIFO mode. */
1041 *reg_mstfctrl &= ~IT8XXX2_SMB_FFEN;
1042 /* Disable I2C write to read FIFO mode. */
1043 if (data->num_msgs == 2) {
1044 i2c_fifo_en_w2r(dev, 0);
1045 }
1046 /* Permit to enter power policy. */
1047 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1048 }
1049 #endif
1050 /* reset i2c channel status */
1051 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
1052 data->i2ccs = I2C_CH_NORMAL;
1053 }
1054 /* Save return value. */
1055 ret = i2c_parsing_return_value(dev);
1056 /* Unlock mutex of i2c controller */
1057 k_mutex_unlock(&data->mutex);
1058
1059 return ret;
1060 }
1061
i2c_it8xxx2_isr(const struct device * dev)1062 static void i2c_it8xxx2_isr(const struct device *dev)
1063 {
1064 struct i2c_it8xxx2_data *data = dev->data;
1065 const struct i2c_it8xxx2_config *config = dev->config;
1066
1067 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1068 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1069
1070 /* If done doing work, wake up the task waiting for the transfer. */
1071 if (config->fifo_enable && (*reg_mstfctrl & IT8XXX2_SMB_FFEN)) {
1072 if (i2c_fifo_transaction(dev)) {
1073 return;
1074 }
1075 } else
1076 #endif
1077 {
1078 if (i2c_pio_transaction(dev)) {
1079 return;
1080 }
1081 }
1082 irq_disable(config->i2c_irq_base);
1083 k_sem_give(&data->device_sync_sem);
1084 }
1085
i2c_it8xxx2_init(const struct device * dev)1086 static int i2c_it8xxx2_init(const struct device *dev)
1087 {
1088 struct i2c_it8xxx2_data *data = dev->data;
1089 const struct i2c_it8xxx2_config *config = dev->config;
1090 uint8_t *base = config->base;
1091 uint32_t bitrate_cfg;
1092 int error, status;
1093
1094 /* Initialize mutex and semaphore */
1095 k_mutex_init(&data->mutex);
1096 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1097
1098 /* Enable clock to specified peripheral */
1099 volatile uint8_t *reg = (volatile uint8_t *)
1100 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1101 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1102 *reg &= ~reg_mask;
1103
1104 /* Enable SMBus function */
1105 /*
1106 * bit0, The SMBus host interface is enabled.
1107 * bit1, Enable to communicate with I2C device
1108 * and support I2C-compatible cycles.
1109 * bit4, This bit controls the reset mechanism
1110 * of SMBus master to handle the SMDAT
1111 * line low if 25ms reg timeout.
1112 */
1113 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN | IT8XXX2_SMB_SMHEN;
1114 /*
1115 * bit1, Kill SMBus host transaction.
1116 * bit0, Enable the interrupt for the master interface.
1117 */
1118 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL | IT8XXX2_SMB_SMHEN;
1119 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SMHEN;
1120
1121 /* W/C host status register */
1122 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
1123 IT8XXX2_SMB_HOCTL2(base) = 0x00;
1124
1125 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1126 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1127
1128 if (config->port == SMB_CHANNEL_B && config->fifo_enable) {
1129 /* Select channel B in FIFO2. */
1130 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_B;
1131 } else if (config->port == SMB_CHANNEL_C && config->fifo_enable) {
1132 /* Select channel C in FIFO2. */
1133 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_C;
1134 }
1135 #endif
1136
1137 /* Set clock frequency for I2C ports */
1138 if (config->bitrate == I2C_BITRATE_STANDARD ||
1139 config->bitrate == I2C_BITRATE_FAST ||
1140 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1141 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1142 } else {
1143 /* Device tree specified speed */
1144 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1145 }
1146
1147 error = i2c_it8xxx2_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1148 data->i2ccs = I2C_CH_NORMAL;
1149
1150 if (error) {
1151 LOG_ERR("i2c: failure initializing");
1152 return error;
1153 }
1154
1155 /* Set the pin to I2C alternate function. */
1156 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1157 if (status < 0) {
1158 LOG_ERR("Failed to configure I2C pins");
1159 return status;
1160 }
1161
1162 return 0;
1163 }
1164
i2c_it8xxx2_recover_bus(const struct device * dev)1165 static int i2c_it8xxx2_recover_bus(const struct device *dev)
1166 {
1167 const struct i2c_it8xxx2_config *config = dev->config;
1168 int i, status;
1169
1170 /* Set SCL of I2C as GPIO pin */
1171 gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT);
1172 /* Set SDA of I2C as GPIO pin */
1173 gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT);
1174
1175 /*
1176 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1177 * is mainly to ensure that gpio has enough time to go from
1178 * low to high or high to low.
1179 */
1180 /* Pull SCL and SDA pin to high */
1181 gpio_pin_set_dt(&config->scl_gpios, 1);
1182 gpio_pin_set_dt(&config->sda_gpios, 1);
1183 k_msleep(1);
1184
1185 /* Start condition */
1186 gpio_pin_set_dt(&config->sda_gpios, 0);
1187 k_msleep(1);
1188 gpio_pin_set_dt(&config->scl_gpios, 0);
1189 k_msleep(1);
1190
1191 /* 9 cycles of SCL with SDA held high */
1192 for (i = 0; i < 9; i++) {
1193 /* SDA */
1194 gpio_pin_set_dt(&config->sda_gpios, 1);
1195 /* SCL */
1196 gpio_pin_set_dt(&config->scl_gpios, 1);
1197 k_msleep(1);
1198 /* SCL */
1199 gpio_pin_set_dt(&config->scl_gpios, 0);
1200 k_msleep(1);
1201 }
1202 /* SDA */
1203 gpio_pin_set_dt(&config->sda_gpios, 0);
1204 k_msleep(1);
1205
1206 /* Stop condition */
1207 gpio_pin_set_dt(&config->scl_gpios, 1);
1208 k_msleep(1);
1209 gpio_pin_set_dt(&config->sda_gpios, 1);
1210 k_msleep(1);
1211
1212 /* Set GPIO back to I2C alternate function of SCL */
1213 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1214 if (status < 0) {
1215 LOG_ERR("Failed to configure I2C pins");
1216 return status;
1217 }
1218
1219 /* reset i2c port */
1220 i2c_reset(dev);
1221 LOG_ERR("I2C ch%d reset cause %d", config->port,
1222 I2C_RC_NO_IDLE_FOR_START);
1223
1224 return 0;
1225 }
1226
1227 static const struct i2c_driver_api i2c_it8xxx2_driver_api = {
1228 .configure = i2c_it8xxx2_configure,
1229 .get_config = i2c_it8xxx2_get_config,
1230 .transfer = i2c_it8xxx2_transfer,
1231 .recover_bus = i2c_it8xxx2_recover_bus,
1232 };
1233
1234 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1235 /*
1236 * Sometimes, channel C may write wrong register to the target device.
1237 * This issue occurs when FIFO2 is enabled on channel C. The problem
1238 * arises because FIFO2 is shared between channel B and channel C.
1239 * FIFO2 will be disabled when data access is completed, at which point
1240 * FIFO2 is set to the default configuration for channel B.
1241 * The byte counter of FIFO2 may be affected by channel B. There is a chance
1242 * that channel C may encounter wrong register being written due to FIFO2
1243 * byte counter wrong write after channel B's write operation.
1244 */
1245 BUILD_ASSERT((DT_INST_PROP(SMB_CHANNEL_C, fifo_enable) == false),
1246 "Channel C cannot use FIFO mode.");
1247 #endif
1248
1249 #define I2C_ITE_IT8XXX2_INIT(inst) \
1250 PINCTRL_DT_INST_DEFINE(inst); \
1251 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1252 50000) || \
1253 (DT_INST_PROP(inst, clock_frequency) == \
1254 I2C_BITRATE_STANDARD) || \
1255 (DT_INST_PROP(inst, clock_frequency) == \
1256 I2C_BITRATE_FAST) || \
1257 (DT_INST_PROP(inst, clock_frequency) == \
1258 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1259 static void i2c_it8xxx2_config_func_##inst(void); \
1260 \
1261 static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##inst = { \
1262 .base = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 0)), \
1263 .reg_mstfctrl = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 1)), \
1264 .irq_config_func = i2c_it8xxx2_config_func_##inst, \
1265 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1266 .i2c_irq_base = DT_INST_IRQN(inst), \
1267 .port = DT_INST_PROP(inst, port_num), \
1268 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1269 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1270 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1271 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1272 .fifo_enable = DT_INST_PROP(inst, fifo_enable), \
1273 }; \
1274 \
1275 static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \
1276 \
1277 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_it8xxx2_init, \
1278 NULL, \
1279 &i2c_it8xxx2_data_##inst, \
1280 &i2c_it8xxx2_cfg_##inst, \
1281 POST_KERNEL, \
1282 CONFIG_I2C_INIT_PRIORITY, \
1283 &i2c_it8xxx2_driver_api); \
1284 \
1285 static void i2c_it8xxx2_config_func_##inst(void) \
1286 { \
1287 IRQ_CONNECT(DT_INST_IRQN(inst), \
1288 0, \
1289 i2c_it8xxx2_isr, \
1290 DEVICE_DT_INST_GET(inst), 0); \
1291 }
1292
1293 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
1294
