1 /*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "analog.h"
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
13
14
15 /* Driver dts compatibility: telink,b91_gpio */
16 #define DT_DRV_COMPAT telink_b91_gpio
17
18 /* Get GPIO instance */
19 #define GET_GPIO(dev) ((volatile struct gpio_b91_t *) \
20 ((const struct gpio_b91_config *)dev->config)->gpio_base)
21
22 /* Get GPIO IRQ number defined in dts */
23 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
24
25 /* Get GPIO IRQ priority defined in dts */
26 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
27
28 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
29 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
30 DT_REG_SIZE(DT_NODELABEL(gpioa))))
31
32 /* Check that gpio is port C */
33 #define IS_PORT_C(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpioc)))
34
35 /* Check that gpio is port D */
36 #define IS_PORT_D(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpiod)))
37
38 /* Check that 'inst' has only 1 interrupt selected in dts */
39 #define IS_INST_IRQ_EN(inst) (DT_NUM_IRQS(DT_DRV_INST(inst)) == 1)
40
41 /* Max pin number per port (pin 0..7) */
42 #define PIN_NUM_MAX ((uint8_t)7u)
43
44 /* IRQ Enable registers */
45 #define reg_irq_risc0_en(i) REG_ADDR8(0x140338 + i)
46 #define reg_irq_risc1_en(i) REG_ADDR8(0x140340 + i)
47
48 /* Pull-up/down resistors */
49 #define GPIO_PIN_UP_DOWN_FLOAT ((uint8_t)0u)
50 #define GPIO_PIN_PULLDOWN_100K ((uint8_t)2u)
51 #define GPIO_PIN_PULLUP_10K ((uint8_t)3u)
52
53 /* GPIO interrupt types */
54 #define INTR_RISING_EDGE ((uint8_t)0u)
55 #define INTR_FALLING_EDGE ((uint8_t)1u)
56 #define INTR_HIGH_LEVEL ((uint8_t)2u)
57 #define INTR_LOW_LEVEL ((uint8_t)3u)
58
59 /* Supported IRQ numbers */
60 #define IRQ_GPIO ((uint8_t)25u)
61 #define IRQ_GPIO2_RISC0 ((uint8_t)26u)
62 #define IRQ_GPIO2_RISC1 ((uint8_t)27u)
63
64
65 /* B91 GPIO registers structure */
66 struct gpio_b91_t {
67 uint8_t input; /* Input: read GPI input */
68 uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
69 uint8_t oen; /* OEN: output enable, low active. 0: enable, 1: disable */
70 uint8_t output; /* Output: configure GPIO output */
71 uint8_t polarity; /* Polarity: interrupt polarity: rising, falling */
72 uint8_t ds; /* DS: drive strength. 1: maximum (default), 0: minimal */
73 uint8_t actas_gpio; /* Act as GPIO: enable (1) or disable (0) GPIO function */
74 uint8_t irq_en; /* Act as GPIO: enable (1) or disable (0) GPIO function */
75 };
76
77 /* GPIO driver configuration structure */
78 struct gpio_b91_config {
79 struct gpio_driver_config common;
80 uint32_t gpio_base;
81 uint32_t irq_num;
82 uint8_t irq_priority;
83 void (*pirq_connect)(void);
84 };
85
86 /* GPIO driver data structure */
87 struct gpio_b91_data {
88 struct gpio_driver_data common; /* driver data */
89 sys_slist_t callbacks; /* list of callbacks */
90 };
91
92
93 /* Set IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_set(const struct device * dev,gpio_pin_t pin)94 static inline void gpiob_b91_irq_en_set(const struct device *dev, gpio_pin_t pin)
95 {
96 uint8_t irq = GET_IRQ_NUM(dev);
97
98 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
99
100 if (irq == IRQ_GPIO) {
101 BM_SET(gpio->irq_en, BIT(pin));
102 } else if (irq == IRQ_GPIO2_RISC0) {
103 BM_SET(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
104 } else if (irq == IRQ_GPIO2_RISC1) {
105 BM_SET(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
106 } else {
107 __ASSERT(false, "Not supported GPIO IRQ number.");
108 }
109 }
110
111 /* Clear IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_clr(const struct device * dev,gpio_pin_t pin)112 static inline void gpiob_b91_irq_en_clr(const struct device *dev, gpio_pin_t pin)
113 {
114 uint8_t irq = GET_IRQ_NUM(dev);
115 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
116
117 if (irq == IRQ_GPIO) {
118 BM_CLR(gpio->irq_en, BIT(pin));
119 } else if (irq == IRQ_GPIO2_RISC0) {
120 BM_CLR(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
121 } else if (irq == IRQ_GPIO2_RISC1) {
122 BM_CLR(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
123 }
124 }
125
126 /* Get IRQ Enable register value */
gpio_b91_irq_en_get(const struct device * dev)127 static inline uint8_t gpio_b91_irq_en_get(const struct device *dev)
128 {
129 uint8_t status = 0;
130 uint8_t irq = GET_IRQ_NUM(dev);
131 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
132
133 if (irq == IRQ_GPIO) {
134 status = gpio->irq_en;
135 } else if (irq == IRQ_GPIO2_RISC0) {
136 status = reg_irq_risc0_en(GET_PORT_NUM(gpio));
137 } else if (irq == IRQ_GPIO2_RISC1) {
138 status = reg_irq_risc1_en(GET_PORT_NUM(gpio));
139 }
140
141 return status;
142 }
143
144 /* Clear IRQ Status bit */
gpio_b91_irq_status_clr(uint8_t irq)145 static inline void gpio_b91_irq_status_clr(uint8_t irq)
146 {
147 gpio_irq_status_e status = 0;
148
149 if (irq == IRQ_GPIO) {
150 status = FLD_GPIO_IRQ_CLR;
151 } else if (irq == IRQ_GPIO2_RISC0) {
152 status = FLD_GPIO_IRQ_GPIO2RISC0_CLR;
153 } else if (irq == IRQ_GPIO2_RISC1) {
154 status = FLD_GPIO_IRQ_GPIO2RISC1_CLR;
155 }
156
157 reg_gpio_irq_clr = status;
158 }
159
160 /* Set pin's irq type */
gpio_b91_irq_set(const struct device * dev,gpio_pin_t pin,uint8_t trigger_type)161 void gpio_b91_irq_set(const struct device *dev, gpio_pin_t pin,
162 uint8_t trigger_type)
163 {
164 uint8_t irq_lvl = 0;
165 uint8_t irq_mask = 0;
166 uint8_t irq_num = GET_IRQ_NUM(dev);
167 uint8_t irq_prioriy = GET_IRQ_PRIORITY(dev);
168 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
169
170 /* Get level and mask based on IRQ number */
171 if (irq_num == IRQ_GPIO) {
172 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO;
173 irq_mask = FLD_GPIO_IRQ_MASK_GPIO;
174 } else if (irq_num == IRQ_GPIO2_RISC0) {
175 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC0;
176 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC0;
177 } else if (irq_num == IRQ_GPIO2_RISC1) {
178 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC1;
179 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC1;
180 }
181
182 /* Set polarity and level */
183 switch (trigger_type) {
184 case INTR_RISING_EDGE:
185 BM_CLR(gpio->polarity, BIT(pin));
186 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
187 break;
188
189 case INTR_FALLING_EDGE:
190 BM_SET(gpio->polarity, BIT(pin));
191 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
192 break;
193
194 case INTR_HIGH_LEVEL:
195 BM_CLR(gpio->polarity, BIT(pin));
196 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
197 break;
198
199 case INTR_LOW_LEVEL:
200 BM_SET(gpio->polarity, BIT(pin));
201 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
202 break;
203 }
204
205 if (irq_num == IRQ_GPIO) {
206 reg_gpio_irq_ctrl |= FLD_GPIO_CORE_INTERRUPT_EN;
207 }
208 gpio_b91_irq_status_clr(irq_num);
209 BM_SET(reg_gpio_irq_risc_mask, irq_mask);
210
211 /* Enable peripheral interrupt */
212 gpiob_b91_irq_en_set(dev, pin);
213
214 /* Enable PLIC interrupt */
215 riscv_plic_irq_enable(irq_num);
216 riscv_plic_set_priority(irq_num, irq_prioriy);
217 }
218
219 /* Set pin's pull-up/down resistor */
gpio_b91_up_down_res_set(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,uint8_t up_down_res)220 static void gpio_b91_up_down_res_set(volatile struct gpio_b91_t *gpio,
221 gpio_pin_t pin,
222 uint8_t up_down_res)
223 {
224 uint8_t val;
225 uint8_t mask;
226 uint8_t analog_reg;
227
228 pin = BIT(pin);
229 val = up_down_res & 0x03;
230 analog_reg = 0x0e + (GET_PORT_NUM(gpio) << 1) + ((pin & 0xf0) ? 1 : 0);
231
232 if (pin & 0x11) {
233 val = val << 0;
234 mask = 0xfc;
235 } else if (pin & 0x22) {
236 val = val << 2;
237 mask = 0xf3;
238 } else if (pin & 0x44) {
239 val = val << 4;
240 mask = 0xcf;
241 } else if (pin & 0x88) {
242 val = val << 6;
243 mask = 0x3f;
244 } else {
245 return;
246 }
247
248 analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val);
249 }
250
251 /* Config Pin pull-up / pull-down resistors */
gpio_b91_config_up_down_res(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)252 static void gpio_b91_config_up_down_res(volatile struct gpio_b91_t *gpio,
253 gpio_pin_t pin,
254 gpio_flags_t flags)
255 {
256 if ((flags & GPIO_PULL_UP) != 0) {
257 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLUP_10K);
258 } else if ((flags & GPIO_PULL_DOWN) != 0) {
259 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLDOWN_100K);
260 } else {
261 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_UP_DOWN_FLOAT);
262 }
263 }
264
265 /* Config Pin In/Out direction */
gpio_b91_config_in_out(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)266 static void gpio_b91_config_in_out(volatile struct gpio_b91_t *gpio,
267 gpio_pin_t pin,
268 gpio_flags_t flags)
269 {
270 uint8_t ie_addr = 0;
271
272 /* Port C and D Input Enable registers are located in another place: analog */
273 if (IS_PORT_C(gpio)) {
274 ie_addr = areg_gpio_pc_ie;
275 } else if (IS_PORT_D(gpio)) {
276 ie_addr = areg_gpio_pd_ie;
277 }
278
279 /* Enable/disable output */
280 WRITE_BIT(gpio->oen, pin, ~flags & GPIO_OUTPUT);
281
282 /* Enable/disable input */
283 if (ie_addr != 0) {
284 /* Port C and D are located in analog space */
285 if (flags & GPIO_INPUT) {
286 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) | BIT(pin));
287 } else {
288 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) & (~BIT(pin)));
289 }
290 } else {
291 /* Input Enable registers of all other ports are located in common GPIO space */
292 WRITE_BIT(gpio->ie, pin, flags & GPIO_INPUT);
293 }
294 }
295
296 /* GPIO driver initialization */
gpio_b91_init(const struct device * dev)297 static int gpio_b91_init(const struct device *dev)
298 {
299 const struct gpio_b91_config *cfg = dev->config;
300
301 cfg->pirq_connect();
302
303 return 0;
304 }
305
306 /* API implementation: pin_configure */
gpio_b91_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)307 static int gpio_b91_pin_configure(const struct device *dev,
308 gpio_pin_t pin,
309 gpio_flags_t flags)
310 {
311 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
312
313 /* Check input parameters: pin number */
314 if (pin > PIN_NUM_MAX) {
315 return -ENOTSUP;
316 }
317
318 /* Check input parameters: open-source and open-drain */
319 if ((flags & GPIO_SINGLE_ENDED) != 0) {
320 return -ENOTSUP;
321 }
322
323 /* Check input parameters: simultaneous in/out mode */
324 if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
325 return -ENOTSUP;
326 }
327
328 /* Set GPIO init state if defined to avoid glitches */
329 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
330 gpio->output |= BIT(pin);
331 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
332 gpio->output &= ~BIT(pin);
333 }
334
335 /* GPIO function enable */
336 WRITE_BIT(gpio->actas_gpio, BIT(pin), 1);
337
338 /* Set GPIO pull-up / pull-down resistors */
339 gpio_b91_config_up_down_res(gpio, pin, flags);
340
341 /* Enable/disable input/output */
342 gpio_b91_config_in_out(gpio, pin, flags);
343
344 return 0;
345 }
346
347 /* API implementation: port_get_raw */
gpio_b91_port_get_raw(const struct device * dev,gpio_port_value_t * value)348 static int gpio_b91_port_get_raw(const struct device *dev,
349 gpio_port_value_t *value)
350 {
351 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
352
353 *value = gpio->input;
354
355 return 0;
356 }
357
358 /* API implementation: port_set_masked_raw */
gpio_b91_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)359 static int gpio_b91_port_set_masked_raw(const struct device *dev,
360 gpio_port_pins_t mask,
361 gpio_port_value_t value)
362 {
363 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
364
365 gpio->output = (gpio->output & ~mask) | (value & mask);
366
367 return 0;
368 }
369
370 /* API implementation: port_set_bits_raw */
gpio_b91_port_set_bits_raw(const struct device * dev,gpio_port_pins_t mask)371 static int gpio_b91_port_set_bits_raw(const struct device *dev,
372 gpio_port_pins_t mask)
373 {
374 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
375
376 gpio->output |= mask;
377
378 return 0;
379 }
380
381 /* API implementation: port_clear_bits_raw */
gpio_b91_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t mask)382 static int gpio_b91_port_clear_bits_raw(const struct device *dev,
383 gpio_port_pins_t mask)
384 {
385 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
386
387 gpio->output &= ~mask;
388
389 return 0;
390 }
391
392 /* API implementation: port_toggle_bits */
gpio_b91_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)393 static int gpio_b91_port_toggle_bits(const struct device *dev,
394 gpio_port_pins_t mask)
395 {
396 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
397
398 gpio->output ^= mask;
399
400 return 0;
401 }
402
403 /* API implementation: interrupts handler */
404 #if IS_INST_IRQ_EN(0) || IS_INST_IRQ_EN(1) || IS_INST_IRQ_EN(2) || \
405 IS_INST_IRQ_EN(3) || IS_INST_IRQ_EN(4)
gpio_b91_irq_handler(const struct device * dev)406 static void gpio_b91_irq_handler(const struct device *dev)
407 {
408 struct gpio_b91_data *data = dev->data;
409 uint8_t irq = GET_IRQ_NUM(dev);
410 uint8_t status = gpio_b91_irq_en_get(dev);
411
412 gpio_b91_irq_status_clr(irq);
413 gpio_fire_callbacks(&data->callbacks, dev, status);
414 }
415 #endif
416
417 /* API implementation: pin_interrupt_configure */
gpio_b91_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)418 static int gpio_b91_pin_interrupt_configure(const struct device *dev,
419 gpio_pin_t pin,
420 enum gpio_int_mode mode,
421 enum gpio_int_trig trig)
422 {
423 int ret_status = 0;
424
425 switch (mode) {
426 case GPIO_INT_MODE_DISABLED: /* GPIO interrupt disable */
427 gpiob_b91_irq_en_clr(dev, pin);
428 break;
429
430 case GPIO_INT_MODE_LEVEL:
431 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt High level */
432 gpio_b91_irq_set(dev, pin, INTR_HIGH_LEVEL);
433 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Low level */
434 gpio_b91_irq_set(dev, pin, INTR_LOW_LEVEL);
435 } else {
436 ret_status = -ENOTSUP;
437 }
438 break;
439
440 case GPIO_INT_MODE_EDGE:
441 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt Rising edge */
442 gpio_b91_irq_set(dev, pin, INTR_RISING_EDGE);
443 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Falling edge */
444 gpio_b91_irq_set(dev, pin, INTR_FALLING_EDGE);
445 } else {
446 ret_status = -ENOTSUP;
447 }
448 break;
449
450 default:
451 ret_status = -ENOTSUP;
452 break;
453 }
454
455 return ret_status;
456 }
457
458 /* API implementation: manage_callback */
gpio_b91_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)459 static int gpio_b91_manage_callback(const struct device *dev,
460 struct gpio_callback *callback,
461 bool set)
462 {
463 struct gpio_b91_data *data = dev->data;
464
465 return gpio_manage_callback(&data->callbacks, callback, set);
466 }
467
468 /* GPIO driver APIs structure */
469 static const struct gpio_driver_api gpio_b91_driver_api = {
470 .pin_configure = gpio_b91_pin_configure,
471 .port_get_raw = gpio_b91_port_get_raw,
472 .port_set_masked_raw = gpio_b91_port_set_masked_raw,
473 .port_set_bits_raw = gpio_b91_port_set_bits_raw,
474 .port_clear_bits_raw = gpio_b91_port_clear_bits_raw,
475 .port_toggle_bits = gpio_b91_port_toggle_bits,
476 .pin_interrupt_configure = gpio_b91_pin_interrupt_configure,
477 .manage_callback = gpio_b91_manage_callback
478 };
479
480 /* If instance 0 is present and has interrupt enabled, connect IRQ */
481 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0
gpio_b91_irq_connect_0(void)482 static void gpio_b91_irq_connect_0(void)
483 {
484 #if IS_INST_IRQ_EN(0)
485 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
486 gpio_b91_irq_handler,
487 DEVICE_DT_INST_GET(0), 0);
488 #endif
489 }
490 #endif
491
492 /* If instance 1 is present and has interrupt enabled, connect IRQ */
493 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
gpio_b91_irq_connect_1(void)494 static void gpio_b91_irq_connect_1(void)
495 {
496 #if IS_INST_IRQ_EN(1)
497 IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
498 gpio_b91_irq_handler,
499 DEVICE_DT_INST_GET(1), 0);
500 #endif
501 }
502 #endif
503
504 /* If instance 2 is present and has interrupt enabled, connect IRQ */
505 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
gpio_b91_irq_connect_2(void)506 static void gpio_b91_irq_connect_2(void)
507 {
508 #if IS_INST_IRQ_EN(2)
509 IRQ_CONNECT(DT_INST_IRQN(2), DT_INST_IRQ(2, priority),
510 gpio_b91_irq_handler,
511 DEVICE_DT_INST_GET(2), 0);
512 #endif
513 }
514 #endif
515
516 /* If instance 3 is present and has interrupt enabled, connect IRQ */
517 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
gpio_b91_irq_connect_3(void)518 static void gpio_b91_irq_connect_3(void)
519 {
520 #if IS_INST_IRQ_EN(3)
521 IRQ_CONNECT(DT_INST_IRQN(3), DT_INST_IRQ(3, priority),
522 gpio_b91_irq_handler,
523 DEVICE_DT_INST_GET(3), 0);
524 #endif
525 }
526 #endif
527
528 /* If instance 4 is present and has interrupt enabled, connect IRQ */
529 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
gpio_b91_irq_connect_4(void)530 static void gpio_b91_irq_connect_4(void)
531 {
532 #if IS_INST_IRQ_EN(4)
533 IRQ_CONNECT(DT_INST_IRQN(4), DT_INST_IRQ(4, priority),
534 gpio_b91_irq_handler,
535 DEVICE_DT_INST_GET(4), 0);
536 #endif
537 }
538 #endif
539
540 /* GPIO driver registration */
541 #define GPIO_B91_INIT(n) \
542 static const struct gpio_b91_config gpio_b91_config_##n = { \
543 .common = { \
544 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
545 }, \
546 .gpio_base = DT_INST_REG_ADDR(n), \
547 .irq_num = DT_INST_IRQN(n), \
548 .irq_priority = DT_INST_IRQ(n, priority), \
549 .pirq_connect = gpio_b91_irq_connect_##n \
550 }; \
551 static struct gpio_b91_data gpio_b91_data_##n; \
552 \
553 DEVICE_DT_INST_DEFINE(n, gpio_b91_init, \
554 NULL, \
555 &gpio_b91_data_##n, \
556 &gpio_b91_config_##n, \
557 PRE_KERNEL_1, \
558 CONFIG_GPIO_INIT_PRIORITY, \
559 &gpio_b91_driver_api);
560
561 DT_INST_FOREACH_STATUS_OKAY(GPIO_B91_INIT)
562
