1 /* 2 * Copyright (c) 2021 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FPGA_EOS_S3_H_ 8 #define ZEPHYR_DRIVERS_FPGA_EOS_S3_H_ 9 10 #include <eoss3_dev.h> 11 12 struct PIF_struct { 13 /* Fabric Configuration Control Register, offset: 0x000 */ 14 __IO uint32_t CFG_CTL; 15 /* Maximum Bit Length Count, offset: 0x004 */ 16 __IO uint32_t MAX_BL_CNT; 17 /* Maximum Word Length Count, offset: 0x008 */ 18 __IO uint32_t MAX_WL_CNT; 19 uint32_t reserved[1020]; 20 /* Configuration Data, offset: 0xFFC */ 21 __IO uint32_t CFG_DATA; 22 }; 23 24 #define PIF ((struct PIF_struct *)PIF_CTRL_BASE) 25 26 #define FB_CFG_ENABLE ((uint32_t)(0x00000200)) 27 #define FB_CFG_DISABLE ((uint32_t)(0x00000000)) 28 29 #define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000)) 30 #define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000)) 31 #define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00)) 32 #define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200)) 33 #define CFG_CTL_APB_BL_SEL ((uint32_t)(0x00000100)) 34 #define CFG_CTL_APB_BLM_SEL ((uint32_t)(0x00000080)) 35 #define CFG_CTL_APB_BR_SEL ((uint32_t)(0x00000040)) 36 #define CFG_CTL_APB_BRM_SEL ((uint32_t)(0x00000020)) 37 #define CFG_CTL_APB_TL_SEL ((uint32_t)(0x00000010)) 38 #define CFG_CTL_APB_TLM_SEL ((uint32_t)(0x00000008)) 39 #define CFG_CTL_APB_TR_SEL ((uint32_t)(0x00000004)) 40 #define CFG_CTL_APB_TRM_SEL ((uint32_t)(0x00000002)) 41 #define CFG_CTL_APB_SEL_CFG ((uint32_t)(0x00000001)) 42 43 #define FB_ISOLATION_ENABLE ((uint32_t)(0x00000001)) 44 #define FB_ISOLATION_DISABLE ((uint32_t)(0x00000000)) 45 46 #define PMU_FFE_FB_PF_SW_PD_FB_PD ((uint32_t)(0x00000002)) 47 #define PMU_FB_PWR_MODE_CFG_FB_SD ((uint32_t)(0x00000002)) 48 #define PMU_FB_PWR_MODE_CFG_FB_DP ((uint32_t)(0x00000001)) 49 50 #define FPGA_INFO \ 51 "eos_s3 eFPGA features:\n" \ 52 "891 Logic Cells\n" \ 53 "8 FIFO Controllers\n" \ 54 "32 Configurable Interfaces\n" \ 55 "2x32x32(or 4x16x16) Multiplier\n" \ 56 "64Kbit SRAM\n" 57 58 #define PAD_ENABLE \ 59 (PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL | PAD_SMT_DISABLE | PAD_REN_DISABLE | \ 60 PAD_SR_SLOW | PAD_CTRL_SEL_AO_REG) 61 62 #define PAD_DISABLE \ 63 (PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW | PAD_E_4MA | PAD_P_PULLDOWN | \ 64 PAD_OEN_NORMAL | PAD_CTRL_SEL_AO_REG) 65 66 #define CFG_CTL_LOAD_ENABLE \ 67 (CFG_CTL_APB_CFG_WR | CFG_CTL_APB_WL_DIN | CFG_CTL_APB_BL_SEL | CFG_CTL_APB_BLM_SEL | \ 68 CFG_CTL_APB_BR_SEL | CFG_CTL_APB_BRM_SEL | CFG_CTL_APB_TL_SEL | CFG_CTL_APB_TLM_SEL | \ 69 CFG_CTL_APB_TR_SEL | CFG_CTL_APB_TRM_SEL | CFG_CTL_APB_SEL_CFG) 70 71 #define CFG_CTL_LOAD_DISABLE 0 72 73 #endif /* ZEPHYR_DRIVERS_FPGA_EOS_S3_H_ */ 74
