1 /* 2 * Copyright (c) 2020 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_EDAC_IBECC_H_ 8 #define ZEPHYR_DRIVERS_EDAC_IBECC_H_ 9 10 /* TODO: Add to include/sys/util.h */ 11 #define BITFIELD(val, h, l) (((val) & GENMASK(h, l)) >> l) 12 13 #define BITFIELD64(val, h, l) (((val) & GENMASK64(h, l)) >> l) 14 15 #define PCI_VENDOR_ID_INTEL 0x8086 16 17 /* Supported SKU map */ 18 #define PCI_DEVICE_ID_SKU5 0x4514 19 #define PCI_DEVICE_ID_SKU6 0x4528 20 #define PCI_DEVICE_ID_SKU7 0x452a 21 #define PCI_DEVICE_ID_SKU8 0x4516 22 #define PCI_DEVICE_ID_SKU9 0x452c 23 #define PCI_DEVICE_ID_SKU10 0x452e 24 #define PCI_DEVICE_ID_SKU11 0x4532 25 #define PCI_DEVICE_ID_SKU12 0x4518 26 #define PCI_DEVICE_ID_SKU13 0x451a 27 #define PCI_DEVICE_ID_SKU14 0x4534 28 #define PCI_DEVICE_ID_SKU15 0x4536 29 30 /* TODO: Move to correct place NMI registers */ 31 32 /* NMI Status and Control Register (NMI_STS_CNT) */ 33 #define NMI_STS_CNT_REG 0x61 34 /* Set by any source of PCH SERR (SERR_NMI_STS) */ 35 #define NMI_STS_SRC_SERR BIT(7) 36 /* Mask for all source bits in the NMI_STS_CNT_REG */ 37 #define NMI_STS_SRC_MASK GENMASK(7, 6) 38 39 /** 40 * Writing 1 SERR NMI are disabled and cleared, writing 0 41 * SERR NMIs are enabled 42 */ 43 #define NMI_STS_SERR_EN BIT(2) 44 /* Mask for all enable bits in the NMI_STS_CNT_REG */ 45 #define NMI_STS_MASK_EN GENMASK(3, 0) 46 47 /** 48 * In-Band Error Correction Code (IBECC) protects data at a cache line 49 * granularity (64 Bytes) with 16 bits SECDED code. 50 * Reports following fields: 51 * - CMI (Converged Memory Interface) Address 52 * - Syndrome 53 * - Error Type (Correctable, Uncorrectable) 54 */ 55 56 /** 57 * PCI Configuration space registers area 58 */ 59 60 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */ 61 #define TOUUD_REG 0x2a 62 #define TOUUD_MASK GENMASK64(38, 20) 63 64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */ 65 #define TOLUD_REG 0x2f 66 #define TOLUD_MASK GENMASK(31, 20) 67 68 /* Total amount of physical memory, offset 0xa0, 64 bit */ 69 #define TOM_REG 0x28 70 #define TOM_MASK GENMASK64(38, 20) 71 72 /* Base address for the Host Memory Mapped Configuration space, 73 * offset 0x48, 64 bit 74 */ 75 #define MCHBAR_REG 0x12 76 #define MCHBAR_MASK GENMASK64(38, 16) 77 #define MCHBAR_ENABLE BIT64(0) 78 /* Size of Host Memory Mapped Configuration space (64K) */ 79 #define MCH_SIZE 0x10000 80 81 /* Capability register, offset 0xec, 32 bit */ 82 #define CAPID0_C_REG 0x3b 83 #define CAPID0_C_IBECC_ENABLED BIT(15) 84 85 /* Register controlling reporting error SERR, offset 0xc8, 16 bit */ 86 #define ERRSTS_REG 0x32 87 #define ERRSTS_IBECC_COR BIT(6) /* Correctable error */ 88 #define ERRSTS_IBECC_UC BIT(7) /* Uncorrectable error */ 89 90 /* Register controlling Host Bridge responses to system errors, 91 * offset 0xca, 16 bit 92 * 93 * TODO: Fix this after PCI access is fixed, now we have to access 94 * ERRSTS_REG with 32 bit access and get this 16 bits 95 */ 96 #define ERRCMD_REG 0x32 97 #define ERRCMD_IBECC_COR BIT(6) /* Correctable error */ 98 #define ERRCMD_IBECC_UC BIT(7) /* Uncorrectable error */ 99 100 /** 101 * Host Memory Mapped Configuration Space (MCHBAR) registers area 102 */ 103 104 #define CHANNEL_HASH 0x5024 105 106 /* ECC Injection Registers */ 107 108 #define IBECC_INJ_ADDR_BASE 0xdd88 109 #define INJ_ADDR_BASE_MASK GENMASK64(38, 6) 110 111 #define IBECC_INJ_ADDR_MASK 0xdd80 112 #define INJ_ADDR_BASE_MASK_MASK GENMASK64(38, 6) 113 114 #define IBECC_INJ_ADDR_CTRL 0xdd98 115 #define INJ_CTRL_COR 0x1 116 #define INJ_CTRL_UC 0x5 117 118 /* Error Logging Registers */ 119 120 /* ECC Error Log register, 64 bit (ECC_ERROR_LOG) */ 121 #define IBECC_ECC_ERROR_LOG 0xdd70 122 /* Uncorrectable (Multiple-bit) Error Status (MERRSTS) */ 123 #define ECC_ERROR_MERRSTS BIT64(63) 124 /* Correctable Error Status (CERRSTS) */ 125 #define ECC_ERROR_CERRSTS BIT64(62) 126 #define ECC_ERROR_ERRTYPE(val) BITFIELD64(val, 63, 62) 127 /* CMI address of the address block of main memory where error happened */ 128 #define ECC_ERROR_ERRADD(val) ((val) & GENMASK64(38, 5)) 129 /* ECC Error Syndrome (ERRSYND) */ 130 #define ECC_ERROR_ERRSYND(val) BITFIELD64(val, 61, 46) 131 132 /* Parity Error Log (PARITY_ERR_LOG) */ 133 #define IBECC_PARITY_ERROR_LOG 0xdd78 134 /* Error Status (ERRSTS) */ 135 #define PARITY_ERROR_ERRSTS BIT64(63) 136 137 /* Memory configuration registers */ 138 139 #define DRAM_MAX_CHANNELS 2 140 #define DRAM_MAX_DIMMS 2 141 142 /* Memory channel decoding register, 32 bit */ 143 #define MAD_INTER_CHAN 0x5000 144 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) 145 /* Enhanced channel mode for LPDDR4 */ 146 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) 147 /* Channel L mapping to physical channel */ 148 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) 149 /* Channel S size in multiples of 0.5GB */ 150 #define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12) 151 152 /* DRAM decode stage 2 registers, 32 bit */ 153 #define MAD_INTRA_CH(index) (0x5004 + index * sizeof(uint32_t)) 154 /* Virtual DIMM L mapping to physical DIMM */ 155 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) 156 157 /* DIMM channel characteristic 2 registers, 32 bit */ 158 #define MAD_DIMM_CH(index) (0x500c + index * sizeof(uint32_t)) 159 /* Size of DIMM L in 0.5GB multiples */ 160 #define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29) 161 /* DIMM L width of DDR chips (DLW) */ 162 #define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7) 163 /* Size of DIMM S in 0.5GB multiples */ 164 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29) 165 /* DIMM S width of DDR chips (DSW) */ 166 #define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24) 167 168 169 /* MC Channel Selection register, 32 bit */ 170 #define CHANNEL_HASH 0x5024 171 172 /* MC Enhanced Channel Selection register, 32 bit */ 173 #define CHANNEL_EHASH 0x5028 174 175 struct ibecc_error { 176 uint32_t type; 177 uint64_t address; 178 uint16_t syndrome; 179 }; 180 181 #define PCI_HOST_BRIDGE PCIE_BDF(0, 0, 0) 182 183 #endif /* ZEPHYR_DRIVERS_EDAC_IBECC_H_ */ 184
