1 /*
2  * Copyright (c) 2020 Kim Bøndergaard <kim@fam-boendergaard.dk>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ST7735R_DISPLAY_DRIVER_H__
7 #define ST7735R_DISPLAY_DRIVER_H__
8 
9 #include <zephyr/kernel.h>
10 
11 #define ST7735R_CMD_SW_RESET            0x01
12 #define ST7735R_CMD_RDDID               0x04
13 #define ST7735R_CMD_RDDST               0x09
14 #define ST7735R_CMD_RDDPM               0x0A
15 #define ST7735R_CMD_RDD_MADCTL          0x0B
16 #define ST7735R_CMD_RDD_COLMOD          0x0C
17 #define ST7735R_CMD_RDDIM               0x0D
18 #define ST7735R_CMD_RDDSM               0x0E
19 
20 #define ST7735R_CMD_SLEEP_IN            0x10
21 #define ST7735R_CMD_SLEEP_OUT           0x11
22 #define ST7735R_CMD_PTLON               0x12
23 #define ST7735R_CMD_NORON               0x13
24 
25 #define ST7735R_CMD_INV_OFF             0x20
26 #define ST7735R_CMD_INV_ON              0x21
27 #define ST7735R_CMD_GAMSET              0x26
28 #define ST7735R_CMD_DISP_OFF            0x28
29 #define ST7735R_CMD_DISP_ON             0x29
30 #define ST7735R_CMD_CASET               0x2a
31 #define ST7735R_CMD_RASET               0x2b
32 #define ST7735R_CMD_RAMWR               0x2c
33 #define ST7735R_CMD_RGBSET              0x2D
34 #define ST7735R_CMD_RAMRD               0x2E
35 
36 #define ST7735R_CMD_PTLAR               0x30
37 #define ST7735R_CMD_TEOFF               0x34
38 #define ST7735R_CMD_TEON                0x35
39 #define ST7735R_CMD_MADCTL              0x36
40 #define ST7735R_CMD_IDMOFF              0x38
41 #define ST7735R_CMD_IDMON               0x39
42 #define ST7735R_CMD_COLMOD              0x3a
43 
44 #define ST7735R_CMD_FRMCTR1             0xB1
45 #define ST7735R_CMD_FRMCTR2             0xB2
46 #define ST7735R_CMD_FRMCTR3             0xB3
47 #define ST7735R_CMD_INVCTR              0xB4
48 
49 #define ST7735R_CMD_PWCTR1              0xC0
50 #define ST7735R_CMD_PWCTR2              0xC1
51 #define ST7735R_CMD_PWCTR3              0xC2
52 #define ST7735R_CMD_PWCTR4              0xC3
53 #define ST7735R_CMD_PWCTR5              0xC4
54 #define ST7735R_CMD_VMCTR1              0xC5
55 #define ST7735R_CMD_VMOFCTR             0xC7
56 
57 #define ST7735R_CMD_WRID2               0xD1
58 #define ST7735R_CMD_WRID3               0xD2
59 #define ST7735R_CMD_NVCTR1              0xD9
60 #define ST7735R_CMD_NVCTR2              0xDE
61 #define ST7735R_CMD_NVCTR3              0xDF
62 #define ST7735R_CMD_RDID1               0xDA
63 #define ST7735R_CMD_RDID2               0xDB
64 #define ST7735R_CMD_RDID3               0xDC
65 #define ST7735R_CMD_NVCTR2              0xDE
66 #define ST7735R_CMD_NVCTR3              0xDF
67 
68 #define ST7735R_CMD_GAMCTRP1            0xE0
69 #define ST7735R_CMD_GAMCTRN1            0xE1
70 
71 /* CMD_MADCTL bits */
72 #define ST7735R_MADCTL_RBG                      0x00
73 #define ST7735R_MADCTL_BGR                      0x08
74 
75 
76 #endif  /* ST7735R_DISPLAY_DRIVER_H__ */
77