1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DAI_PARAMS_INTEL_IPC4_H__ 8 #define __DAI_PARAMS_INTEL_IPC4_H__ 9 10 #include <stdint.h> 11 12 #define DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT 8 13 14 /**< Type of the gateway. */ 15 enum dai_intel_ipc4_connector_node_id_type { 16 /**< HD/A host output (-> DSP). */ 17 dai_intel_ipc4_hda_host_output_class = 0, 18 /**< HD/A host input (<- DSP). */ 19 dai_intel_ipc4_hda_host_input_class = 1, 20 /**< HD/A host input/output (rsvd for future use). */ 21 dai_intel_ipc4_hda_host_inout_class = 2, 22 23 /**< HD/A link output (DSP ->). */ 24 dai_intel_ipc4_hda_link_output_class = 8, 25 /**< HD/A link input (DSP <-). */ 26 dai_intel_ipc4_hda_link_input_class = 9, 27 /**< HD/A link input/output (rsvd for future use). */ 28 dai_intel_ipc4_hda_link_inout_class = 10, 29 30 /**< DMIC link input (DSP <-). */ 31 dai_intel_ipc4_dmic_link_input_class = 11, 32 33 /**< I2S link output (DSP ->). */ 34 dai_intel_ipc4_i2s_link_output_class = 12, 35 /**< I2S link input (DSP <-). */ 36 dai_intel_ipc4_i2s_link_input_class = 13, 37 38 /**< ALH link output, legacy for SNDW (DSP ->). */ 39 dai_intel_ipc4_alh_link_output_class = 16, 40 /**< ALH link input, legacy for SNDW (DSP <-). */ 41 dai_intel_ipc4_alh_link_input_class = 17, 42 43 /**< SNDW link output (DSP ->). */ 44 dai_intel_ipc4_alh_snd_wire_stream_link_output_class = 16, 45 /**< SNDW link input (DSP <-). */ 46 dai_intel_ipc4_alh_snd_wire_stream_link_input_class = 17, 47 48 /**< UAOL link output (DSP ->). */ 49 dai_intel_ipc4_alh_uaol_stream_link_output_class = 18, 50 /**< UAOL link input (DSP <-). */ 51 dai_intel_ipc4_alh_uaol_stream_link_input_class = 19, 52 53 /**< IPC output (DSP ->). */ 54 dai_intel_ipc4_ipc_output_class = 20, 55 /**< IPC input (DSP <-). */ 56 dai_intel_ipc4_ipc_input_class = 21, 57 58 /**< I2S Multi gtw output (DSP ->). */ 59 dai_intel_ipc4_i2s_multi_link_output_class = 22, 60 /**< I2S Multi gtw input (DSP <-). */ 61 dai_intel_ipc4_i2s_multi_link_input_class = 23, 62 /**< GPIO */ 63 dai_intel_ipc4_gpio_class = 24, 64 /**< SPI */ 65 dai_intel_ipc4_spi_output_class = 25, 66 dai_intel_ipc4_spi_input_class = 26, 67 dai_intel_ipc4_max_connector_node_id_type 68 }; 69 70 struct ssp_intel_aux_tlv { 71 uint32_t type; 72 uint32_t size; 73 uint32_t val[]; 74 } __packed; 75 76 struct ssp_intel_mn_ctl { 77 uint32_t div_m; 78 uint32_t div_n; 79 } __packed; 80 81 struct ssp_intel_clk_ctl { 82 uint32_t start; 83 uint32_t stop; 84 } __packed; 85 86 struct ssp_intel_tr_ctl { 87 uint32_t sampling_frequency; 88 uint32_t bit_depth; 89 uint32_t channel_map; 90 uint32_t channel_config; 91 uint32_t interleaving_style; 92 uint32_t format; 93 } __packed; 94 95 struct ssp_intel_run_ctl { 96 uint32_t enabled; 97 } __packed; 98 99 struct ssp_intel_node_ctl { 100 uint32_t node_id; 101 uint32_t sampling_rate; 102 } __packed; 103 104 struct ssp_intel_sync_ctl { 105 uint32_t sync_denominator; 106 uint32_t count; 107 } __packed; 108 109 struct ssp_intel_ext_ctl { 110 uint32_t ext_data; 111 } __packed; 112 113 struct ssp_intel_link_ctl { 114 uint32_t clock_source; 115 } __packed; 116 117 #define SSP_MN_DIVIDER_CONTROLS 0 118 #define SSP_DMA_CLK_CONTROLS 1 119 #define SSP_DMA_TRANSMISSION_START 2 120 #define SSP_DMA_TRANSMISSION_STOP 3 121 #define SSP_DMA_ALWAYS_RUNNING_MODE 4 122 #define SSP_DMA_SYNC_DATA 5 123 #define SSP_DMA_CLK_CONTROLS_EXT 6 124 #define SSP_LINK_CLK_SOURCE 7 125 126 /**< Base top-level structure of an address of a gateway. */ 127 /*! 128 * The virtual index value, presented on the top level as raw 8 bits, 129 * is expected to be encoded in a gateway specific way depending on 130 * the actual type of gateway. 131 */ 132 union dai_intel_ipc4_connector_node_id { 133 134 /**< Raw 32-bit value of node id. */ 135 uint32_t dw; 136 137 /**< Bit fields */ 138 struct { 139 /**< Index of the virtual DMA at the gateway. */ 140 uint32_t v_index : 8; 141 142 /**< Type of the gateway, one of ConnectorNodeId::Type values. */ 143 uint32_t dma_type : 5; 144 145 /**< Rsvd field. */ 146 uint32_t _rsvd : 19; 147 } f; /**<< Bits */ 148 } __packed; 149 150 /*! 151 * Attributes are usually provided along with the gateway configuration 152 * BLOB when the FW is requested to instantiate that gateway. 153 * 154 * There are flags which requests FW to allocate gateway related data 155 * (buffers and other items used while transferring data, like linked list) 156 * to be allocated from a special memory area, e.g low power memory. 157 */ 158 union dai_intel_ipc4_gateway_attributes { 159 160 /**< Raw value */ 161 uint32_t dw; 162 163 /**< Access to the fields */ 164 struct { 165 /**< Gateway data requested in low power memory. */ 166 uint32_t lp_buffer_alloc : 1; 167 168 /**< Gateway data requested in register file memory. */ 169 uint32_t alloc_from_reg_file : 1; 170 171 /**< Reserved field */ 172 uint32_t _rsvd : 30; 173 } bits; /**<< Bits */ 174 } __packed; 175 176 /**< Configuration for the IPC Gateway */ 177 struct dai_intel_ipc4_gateway_config_blob { 178 179 /**< Size of the gateway buffer, specified in bytes */ 180 uint32_t buffer_size; 181 182 /**< Flags */ 183 union flags { 184 struct bits { 185 /**< Activates high threshold notification */ 186 /*! 187 * Indicates whether notification should be sent to the host 188 * when the size of data in the buffer reaches the high threshold 189 * specified by threshold_high parameter. 190 */ 191 uint32_t notif_high : 1; 192 193 /**< Activates low threshold notification */ 194 /*! 195 * Indicates whether notification should be sent to the host 196 * when the size of data in the buffer reaches the low threshold 197 * specified by threshold_low parameter. 198 */ 199 uint32_t notif_low : 1; 200 201 /**< Reserved field */ 202 uint32_t rsvd : 30; 203 } f; /**<< Bits */ 204 /**< Raw value of flags */ 205 uint32_t flags_raw; 206 } u; /**<< Flags */ 207 208 /**< High threshold */ 209 /*! 210 * Specifies the high threshold (in bytes) for notifying the host 211 * about the buffered data level. 212 */ 213 uint32_t threshold_high; 214 215 /**< Low threshold */ 216 /*! 217 * Specifies the low threshold (in bytes) for notifying the host 218 * about the buffered data level. 219 */ 220 uint32_t threshold_low; 221 } __packed; 222 223 /* i2s Configuration BLOB building blocks */ 224 225 /* i2s registers for i2s Configuration */ 226 struct dai_intel_ipc4_ssp_config { 227 uint32_t ssc0; 228 uint32_t ssc1; 229 uint32_t sscto; 230 uint32_t sspsp; 231 uint32_t sstsa; 232 uint32_t ssrsa; 233 uint32_t ssc2; 234 uint32_t sspsp2; 235 uint32_t ssc3; 236 uint32_t ssioc; 237 } __packed; 238 239 struct dai_intel_ipc4_ssp_mclk_config { 240 /* master clock divider control register */ 241 uint32_t mdivc; 242 243 /* master clock divider ratio register */ 244 uint32_t mdivr; 245 } __packed; 246 247 struct dai_intel_ipc4_ssp_mclk_config_2 { 248 uint32_t mdivctlr; 249 uint32_t mdivrcnt; 250 uint32_t mdivr[]; 251 } __packed; 252 253 struct dai_intel_ipc4_ssp_driver_config { 254 struct dai_intel_ipc4_ssp_config i2s_config; 255 struct dai_intel_ipc4_ssp_mclk_config mclk_config; 256 } __packed; 257 258 struct dai_intel_ipc4_ssp_start_control { 259 /* delay in msec between enabling interface (moment when 260 * Copier instance is being attached to the interface) and actual 261 * interface start. Value of 0 means no delay. 262 */ 263 uint32_t clock_warm_up : 16; 264 265 /* specifies if parameters target MCLK (1) or SCLK (0) */ 266 uint32_t mclk : 1; 267 268 /* value of 1 means that clock should be started immediately 269 * even if no Copier instance is currently attached to the interface. 270 */ 271 uint32_t warm_up_ovr : 1; 272 uint32_t rsvd0 : 14; 273 } __packed; 274 275 struct dai_intel_ipc4_ssp_stop_control { 276 /* delay in msec between stopping the interface 277 * (moment when Copier instance is being detached from the interface) 278 * and interface clock stop. Value of 0 means no delay. 279 */ 280 uint32_t clock_stop_delay : 16; 281 282 /* value of 1 means that clock should be kept running (infinite 283 * stop delay) after Copier instance detaches from the interface. 284 */ 285 uint32_t keep_running : 1; 286 287 /* value of 1 means that clock should be stopped immediately */ 288 uint32_t clock_stop_ovr : 1; 289 uint32_t rsvd1 : 14; 290 } __packed; 291 292 union dai_intel_ipc4_ssp_dma_control { 293 struct dai_intel_ipc4_ssp_control { 294 struct dai_intel_ipc4_ssp_start_control start_control; 295 struct dai_intel_ipc4_ssp_stop_control stop_control; 296 } control_data; 297 298 struct dai_intel_ipc4_mn_div_config { 299 uint32_t mval; 300 uint32_t nval; 301 } mndiv_control_data; 302 } __packed; 303 304 struct dai_intel_ipc4_ssp_configuration_blob { 305 union dai_intel_ipc4_gateway_attributes gw_attr; 306 307 /* TDM time slot mappings */ 308 uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; 309 310 /* i2s port configuration */ 311 struct dai_intel_ipc4_ssp_driver_config i2s_driver_config; 312 313 /* optional configuration parameters */ 314 union dai_intel_ipc4_ssp_dma_control i2s_dma_control[0]; 315 } __packed; 316 317 #define SSP_BLOB_VER_1_5 0xee000105 318 319 struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 { 320 union dai_intel_ipc4_gateway_attributes gw_attr; 321 322 uint32_t version; 323 uint32_t size; 324 325 /* TDM time slot mappings */ 326 uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; 327 328 /* i2s port configuration */ 329 struct dai_intel_ipc4_ssp_config i2s_ssp_config; 330 /* clock configuration parameters */ 331 struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control; 332 } __packed; 333 334 #endif 335
