1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DAI_PARAMS_INTEL_IPC3_H__ 8 #define __DAI_PARAMS_INTEL_IPC3_H__ 9 10 #include <stdint.h> 11 12 #define DAI_INTEL_IPC3_SSP_FMT_I2S 1 /**< I2S mode */ 13 #define DAI_INTEL_IPC3_SSP_FMT_RIGHT_J 2 /**< Right Justified mode */ 14 #define DAI_INTEL_IPC3_SSP_FMT_LEFT_J 3 /**< Left Justified mode */ 15 #define DAI_INTEL_IPC3_SSP_FMT_DSP_A 4 /**< L data MSB after FRM LRC */ 16 #define DAI_INTEL_IPC3_SSP_FMT_DSP_B 5 /**< L data MSB during FRM LRC */ 17 #define DAI_INTEL_IPC3_SSP_FMT_PDM 6 /**< Pulse density modulation */ 18 19 #define DAI_INTEL_IPC3_SSP_FMT_CONT (1 << 4) /**< continuous clock */ 20 #define DAI_INTEL_IPC3_SSP_FMT_GATED (0 << 4) /**< clock is gated */ 21 22 #define DAI_INTEL_IPC3_SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */ 23 #define DAI_INTEL_IPC3_SSP_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */ 24 #define DAI_INTEL_IPC3_SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */ 25 #define DAI_INTEL_IPC3_SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */ 26 27 #define DAI_INTEL_IPC3_SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */ 28 #define DAI_INTEL_IPC3_SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */ 29 #define DAI_INTEL_IPC3_SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */ 30 #define DAI_INTEL_IPC3_SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */ 31 32 #define DAI_INTEL_IPC3_SSP_FMT_FORMAT_MASK 0x000f 33 #define DAI_INTEL_IPC3_SSP_FMT_CLOCK_MASK 0x00f0 34 #define DAI_INTEL_IPC3_SSP_FMT_INV_MASK 0x0f00 35 #define DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK 0xf000 36 37 /* 38 * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE 39 * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above 40 * commands. 41 */ 42 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_CMD_MASK 0xF 43 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_NONE 0 /**< config without stage information */ 44 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< config during hw_params stage */ 45 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_FREE BIT(1) /**< config during hw_free stage */ 46 47 /**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */ 48 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_PAUSE BIT(2) 49 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_SHIFT 4 50 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT) 51 /* 52 * This should be used along with the DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS to indicate that 53 * pipeline stop/pause and DAI DMA stop/pause should happen in two steps. This change is only 54 * available ABI 3.20 onwards. 55 */ 56 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_2_STEP_STOP BIT(0) 57 58 /* ssc1: TINTE */ 59 #define DAI_INTEL_IPC3_SSP_QUIRK_TINTE (1 << 0) 60 /* ssc1: PINTE */ 61 #define DAI_INTEL_IPC3_SSP_QUIRK_PINTE (1 << 1) 62 /* ssc2: SMTATF */ 63 #define DAI_INTEL_IPC3_SSP_QUIRK_SMTATF (1 << 2) 64 /* ssc2: MMRATF */ 65 #define DAI_INTEL_IPC3_SSP_QUIRK_MMRATF (1 << 3) 66 /* ssc2: PSPSTWFDFD */ 67 #define DAI_INTEL_IPC3_SSP_QUIRK_PSPSTWFDFD (1 << 4) 68 /* ssc2: PSPSRWFDFD */ 69 #define DAI_INTEL_IPC3_SSP_QUIRK_PSPSRWFDFD (1 << 5) 70 /* ssc1: LBM */ 71 #define DAI_INTEL_IPC3_SSP_QUIRK_LBM (1 << 6) 72 73 /* here is the possibility to define others aux macros */ 74 75 #define DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX 38 76 #define DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX 31 77 78 /* SSP clocks control settings 79 * 80 * Macros for clks_control field in sof_dai_ssp_params struct. 81 */ 82 83 /* mclk 0 disable */ 84 #define DAI_INTEL_IPC3_SSP_MCLK_0_DISABLE BIT(0) 85 /* mclk 1 disable */ 86 #define DAI_INTEL_IPC3_SSP_MCLK_1_DISABLE BIT(1) 87 /* mclk keep active */ 88 #define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_KA BIT(2) 89 /* bclk keep active */ 90 #define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_KA BIT(3) 91 /* fs keep active */ 92 #define DAI_INTEL_IPC3_SSP_CLKCTRL_FS_KA BIT(4) 93 /* bclk idle */ 94 #define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 95 /* mclk early start */ 96 #define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_ES BIT(6) 97 /* bclk early start */ 98 #define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_ES BIT(7) 99 100 /* SSP Configuration Request - SOF_DAI_SSP_CONFIG */ 101 struct dai_intel_ipc3_ssp_params { 102 uint32_t reserved0; 103 uint16_t reserved1; 104 uint16_t mclk_id; 105 106 uint32_t mclk_rate; /* mclk frequency in Hz */ 107 uint32_t fsync_rate; /* fsync frequency in Hz */ 108 uint32_t bclk_rate; /* bclk frequency in Hz */ 109 110 /* TDM */ 111 uint32_t tdm_slots; 112 uint32_t rx_slots; 113 uint32_t tx_slots; 114 115 /* data */ 116 uint32_t sample_valid_bits; 117 uint16_t tdm_slot_width; 118 uint16_t reserved2; /* alignment */ 119 120 /* MCLK */ 121 uint32_t mclk_direction; 122 123 uint16_t frame_pulse_width; 124 uint16_t tdm_per_slot_padding_flag; 125 uint32_t clks_control; 126 uint32_t quirks; 127 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 128 * will be driven, before sending data 129 */ 130 } __packed; 131 132 #endif /* __DAI_PARAMS_INTEL_IPC3_H__ */ 133
