1 /*
2 * Copyright (c) 2018 Alexander Wachter
3 * Copyright (c) 2022 Martin Jäger <martin@libre.solar>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can/transceiver.h>
9 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/sys/util.h>
13 #include <string.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <errno.h>
17 #include <stdbool.h>
18 #include <zephyr/drivers/can.h>
19 #include <zephyr/logging/log.h>
20 #include <zephyr/irq.h>
21
22 LOG_MODULE_REGISTER(can_stm32, CONFIG_CAN_LOG_LEVEL);
23
24 #define CAN_INIT_TIMEOUT (10 * (sys_clock_hw_cycles_per_sec() / MSEC_PER_SEC))
25
26 #define DT_DRV_COMPAT st_stm32_bxcan
27
28 #define SP_IS_SET(inst) DT_INST_NODE_HAS_PROP(inst, sample_point) ||
29
30 /* Macro to exclude the sample point algorithm from compilation if not used
31 * Without the macro, the algorithm would always waste ROM
32 */
33 #define USE_SP_ALGO (DT_INST_FOREACH_STATUS_OKAY(SP_IS_SET) 0)
34
35 #define SP_AND_TIMING_NOT_SET(inst) \
36 (!DT_INST_NODE_HAS_PROP(inst, sample_point) && \
37 !(DT_INST_NODE_HAS_PROP(inst, prop_seg) && \
38 DT_INST_NODE_HAS_PROP(inst, phase_seg1) && \
39 DT_INST_NODE_HAS_PROP(inst, phase_seg2))) ||
40
41 #if DT_INST_FOREACH_STATUS_OKAY(SP_AND_TIMING_NOT_SET) 0
42 #error You must either set a sampling-point or timings (phase-seg* and prop-seg)
43 #endif
44
45 #define CAN_STM32_NUM_FILTER_BANKS (14)
46 #define CAN_STM32_MAX_FILTER_ID \
47 (CONFIG_CAN_MAX_EXT_ID_FILTER + CONFIG_CAN_MAX_STD_ID_FILTER * 2)
48
49 #define CAN_STM32_FIRX_STD_IDE_POS (3U)
50 #define CAN_STM32_FIRX_STD_RTR_POS (4U)
51 #define CAN_STM32_FIRX_STD_ID_POS (5U)
52
53 #define CAN_STM32_FIRX_EXT_IDE_POS (2U)
54 #define CAN_STM32_FIRX_EXT_RTR_POS (1U)
55 #define CAN_STM32_FIRX_EXT_STD_ID_POS (21U)
56 #define CAN_STM32_FIRX_EXT_EXT_ID_POS (3U)
57
58 #if (CONFIG_CAN_MAX_STD_ID_FILTER + CONFIG_CAN_MAX_EXT_ID_FILTER * 2) > \
59 (CAN_STM32_NUM_FILTER_BANKS * 2)
60 #error Number of configured filters exceeds available filter bank slots.
61 #endif
62
63 struct can_stm32_mailbox {
64 can_tx_callback_t tx_callback;
65 void *callback_arg;
66 };
67
68 struct can_stm32_data {
69 struct k_mutex inst_mutex;
70 struct k_sem tx_int_sem;
71 struct can_stm32_mailbox mb0;
72 struct can_stm32_mailbox mb1;
73 struct can_stm32_mailbox mb2;
74 can_rx_callback_t rx_cb_std[CONFIG_CAN_MAX_STD_ID_FILTER];
75 can_rx_callback_t rx_cb_ext[CONFIG_CAN_MAX_EXT_ID_FILTER];
76 void *cb_arg_std[CONFIG_CAN_MAX_STD_ID_FILTER];
77 void *cb_arg_ext[CONFIG_CAN_MAX_EXT_ID_FILTER];
78 can_state_change_callback_t state_change_cb;
79 void *state_change_cb_data;
80 enum can_state state;
81 bool started;
82 };
83
84 struct can_stm32_config {
85 CAN_TypeDef *can; /*!< CAN Registers*/
86 CAN_TypeDef *master_can; /*!< CAN Registers for shared filter */
87 uint32_t bus_speed;
88 uint16_t sample_point;
89 uint8_t sjw;
90 uint8_t prop_ts1;
91 uint8_t ts2;
92 struct stm32_pclken pclken;
93 void (*config_irq)(CAN_TypeDef *can);
94 const struct pinctrl_dev_config *pcfg;
95 const struct device *phy;
96 uint32_t max_bitrate;
97 };
98
99 /*
100 * Mutex to prevent simultaneous access to filter registers shared between CAN1
101 * and CAN2.
102 */
103 static struct k_mutex filter_mutex;
104
can_stm32_signal_tx_complete(const struct device * dev,struct can_stm32_mailbox * mb,int status)105 static void can_stm32_signal_tx_complete(const struct device *dev, struct can_stm32_mailbox *mb,
106 int status)
107 {
108 can_tx_callback_t callback = mb->tx_callback;
109
110 if (callback != NULL) {
111 callback(dev, status, mb->callback_arg);
112 mb->tx_callback = NULL;
113 }
114 }
115
can_stm32_rx_fifo_pop(CAN_FIFOMailBox_TypeDef * mbox,struct can_frame * frame)116 static void can_stm32_rx_fifo_pop(CAN_FIFOMailBox_TypeDef *mbox, struct can_frame *frame)
117 {
118 memset(frame, 0, sizeof(*frame));
119
120 if (mbox->RIR & CAN_RI0R_IDE) {
121 frame->id = mbox->RIR >> CAN_RI0R_EXID_Pos;
122 frame->flags |= CAN_FRAME_IDE;
123 } else {
124 frame->id = mbox->RIR >> CAN_RI0R_STID_Pos;
125 }
126
127 if ((mbox->RIR & CAN_RI0R_RTR) != 0) {
128 frame->flags |= CAN_FRAME_RTR;
129 } else {
130 frame->data_32[0] = mbox->RDLR;
131 frame->data_32[1] = mbox->RDHR;
132 }
133
134 frame->dlc = mbox->RDTR & (CAN_RDT0R_DLC >> CAN_RDT0R_DLC_Pos);
135 #ifdef CONFIG_CAN_RX_TIMESTAMP
136 frame->timestamp = ((mbox->RDTR & CAN_RDT0R_TIME) >> CAN_RDT0R_TIME_Pos);
137 #endif
138 }
139
can_stm32_rx_isr_handler(const struct device * dev)140 static inline void can_stm32_rx_isr_handler(const struct device *dev)
141 {
142 struct can_stm32_data *data = dev->data;
143 const struct can_stm32_config *cfg = dev->config;
144 CAN_TypeDef *can = cfg->can;
145 CAN_FIFOMailBox_TypeDef *mbox;
146 int filter_id, index;
147 struct can_frame frame;
148 can_rx_callback_t callback = NULL;
149 void *cb_arg;
150
151 while (can->RF0R & CAN_RF0R_FMP0) {
152 mbox = &can->sFIFOMailBox[0];
153 filter_id = ((mbox->RDTR & CAN_RDT0R_FMI) >> CAN_RDT0R_FMI_Pos);
154
155 LOG_DBG("Message on filter_id %d", filter_id);
156
157 can_stm32_rx_fifo_pop(mbox, &frame);
158
159 if (filter_id < CONFIG_CAN_MAX_EXT_ID_FILTER) {
160 callback = data->rx_cb_ext[filter_id];
161 cb_arg = data->cb_arg_ext[filter_id];
162 } else if (filter_id < CAN_STM32_MAX_FILTER_ID) {
163 index = filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER;
164 callback = data->rx_cb_std[index];
165 cb_arg = data->cb_arg_std[index];
166 }
167
168 if (callback) {
169 callback(dev, &frame, cb_arg);
170 }
171
172 /* Release message */
173 can->RF0R |= CAN_RF0R_RFOM0;
174 }
175
176 if (can->RF0R & CAN_RF0R_FOVR0) {
177 LOG_ERR("RX FIFO Overflow");
178 CAN_STATS_RX_OVERRUN_INC(dev);
179 }
180 }
181
can_stm32_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)182 static int can_stm32_get_state(const struct device *dev, enum can_state *state,
183 struct can_bus_err_cnt *err_cnt)
184 {
185 const struct can_stm32_config *cfg = dev->config;
186 struct can_stm32_data *data = dev->data;
187 CAN_TypeDef *can = cfg->can;
188
189 if (state != NULL) {
190 if (!data->started) {
191 *state = CAN_STATE_STOPPED;
192 } else if (can->ESR & CAN_ESR_BOFF) {
193 *state = CAN_STATE_BUS_OFF;
194 } else if (can->ESR & CAN_ESR_EPVF) {
195 *state = CAN_STATE_ERROR_PASSIVE;
196 } else if (can->ESR & CAN_ESR_EWGF) {
197 *state = CAN_STATE_ERROR_WARNING;
198 } else {
199 *state = CAN_STATE_ERROR_ACTIVE;
200 }
201 }
202
203 if (err_cnt != NULL) {
204 err_cnt->tx_err_cnt =
205 ((can->ESR & CAN_ESR_TEC) >> CAN_ESR_TEC_Pos);
206 err_cnt->rx_err_cnt =
207 ((can->ESR & CAN_ESR_REC) >> CAN_ESR_REC_Pos);
208 }
209
210 return 0;
211 }
212
can_stm32_bus_state_change_isr(const struct device * dev)213 static inline void can_stm32_bus_state_change_isr(const struct device *dev)
214 {
215 struct can_stm32_data *data = dev->data;
216 struct can_bus_err_cnt err_cnt;
217 enum can_state state;
218 const can_state_change_callback_t cb = data->state_change_cb;
219 void *state_change_cb_data = data->state_change_cb_data;
220
221 #ifdef CONFIG_CAN_STATS
222 const struct can_stm32_config *cfg = dev->config;
223 CAN_TypeDef *can = cfg->can;
224
225 switch (can->ESR & CAN_ESR_LEC) {
226 case (CAN_ESR_LEC_0):
227 CAN_STATS_STUFF_ERROR_INC(dev);
228 break;
229 case (CAN_ESR_LEC_1):
230 CAN_STATS_FORM_ERROR_INC(dev);
231 break;
232 case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
233 CAN_STATS_ACK_ERROR_INC(dev);
234 break;
235 case (CAN_ESR_LEC_2):
236 CAN_STATS_BIT1_ERROR_INC(dev);
237 break;
238 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
239 CAN_STATS_BIT0_ERROR_INC(dev);
240 break;
241 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
242 CAN_STATS_CRC_ERROR_INC(dev);
243 break;
244 default:
245 break;
246 }
247
248 /* Clear last error code flag */
249 can->ESR |= CAN_ESR_LEC;
250 #endif /* CONFIG_CAN_STATS */
251
252 (void)can_stm32_get_state(dev, &state, &err_cnt);
253
254 if (state != data->state) {
255 data->state = state;
256
257 if (cb != NULL) {
258 cb(dev, state, err_cnt, state_change_cb_data);
259 }
260 }
261 }
262
can_stm32_tx_isr_handler(const struct device * dev)263 static inline void can_stm32_tx_isr_handler(const struct device *dev)
264 {
265 struct can_stm32_data *data = dev->data;
266 const struct can_stm32_config *cfg = dev->config;
267 CAN_TypeDef *can = cfg->can;
268 uint32_t bus_off;
269 int status;
270
271 bus_off = can->ESR & CAN_ESR_BOFF;
272
273 if ((can->TSR & CAN_TSR_RQCP0) | bus_off) {
274 status = can->TSR & CAN_TSR_TXOK0 ? 0 :
275 can->TSR & CAN_TSR_TERR0 ? -EIO :
276 can->TSR & CAN_TSR_ALST0 ? -EBUSY :
277 bus_off ? -ENETUNREACH :
278 -EIO;
279 /* clear the request. */
280 can->TSR |= CAN_TSR_RQCP0;
281 can_stm32_signal_tx_complete(dev, &data->mb0, status);
282 }
283
284 if ((can->TSR & CAN_TSR_RQCP1) | bus_off) {
285 status = can->TSR & CAN_TSR_TXOK1 ? 0 :
286 can->TSR & CAN_TSR_TERR1 ? -EIO :
287 can->TSR & CAN_TSR_ALST1 ? -EBUSY :
288 bus_off ? -ENETUNREACH :
289 -EIO;
290 /* clear the request. */
291 can->TSR |= CAN_TSR_RQCP1;
292 can_stm32_signal_tx_complete(dev, &data->mb1, status);
293 }
294
295 if ((can->TSR & CAN_TSR_RQCP2) | bus_off) {
296 status = can->TSR & CAN_TSR_TXOK2 ? 0 :
297 can->TSR & CAN_TSR_TERR2 ? -EIO :
298 can->TSR & CAN_TSR_ALST2 ? -EBUSY :
299 bus_off ? -ENETUNREACH :
300 -EIO;
301 /* clear the request. */
302 can->TSR |= CAN_TSR_RQCP2;
303 can_stm32_signal_tx_complete(dev, &data->mb2, status);
304 }
305
306 if (can->TSR & CAN_TSR_TME) {
307 k_sem_give(&data->tx_int_sem);
308 }
309 }
310
311 #ifdef CONFIG_SOC_SERIES_STM32F0X
312
can_stm32_isr(const struct device * dev)313 static void can_stm32_isr(const struct device *dev)
314 {
315 const struct can_stm32_config *cfg = dev->config;
316 CAN_TypeDef *can = cfg->can;
317
318 can_stm32_tx_isr_handler(dev);
319 can_stm32_rx_isr_handler(dev);
320
321 if (can->MSR & CAN_MSR_ERRI) {
322 can_stm32_bus_state_change_isr(dev);
323 can->MSR |= CAN_MSR_ERRI;
324 }
325 }
326
327 #else
328
can_stm32_rx_isr(const struct device * dev)329 static void can_stm32_rx_isr(const struct device *dev)
330 {
331 can_stm32_rx_isr_handler(dev);
332 }
333
can_stm32_tx_isr(const struct device * dev)334 static void can_stm32_tx_isr(const struct device *dev)
335 {
336 can_stm32_tx_isr_handler(dev);
337 }
338
can_stm32_state_change_isr(const struct device * dev)339 static void can_stm32_state_change_isr(const struct device *dev)
340 {
341 const struct can_stm32_config *cfg = dev->config;
342 CAN_TypeDef *can = cfg->can;
343
344 /* Signal bus-off to waiting tx */
345 if (can->MSR & CAN_MSR_ERRI) {
346 can_stm32_tx_isr_handler(dev);
347 can_stm32_bus_state_change_isr(dev);
348 can->MSR |= CAN_MSR_ERRI;
349 }
350 }
351
352 #endif
353
can_stm32_enter_init_mode(CAN_TypeDef * can)354 static int can_stm32_enter_init_mode(CAN_TypeDef *can)
355 {
356 uint32_t start_time;
357
358 can->MCR |= CAN_MCR_INRQ;
359 start_time = k_cycle_get_32();
360
361 while ((can->MSR & CAN_MSR_INAK) == 0U) {
362 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
363 can->MCR &= ~CAN_MCR_INRQ;
364 return -EAGAIN;
365 }
366 }
367
368 return 0;
369 }
370
can_stm32_leave_init_mode(CAN_TypeDef * can)371 static int can_stm32_leave_init_mode(CAN_TypeDef *can)
372 {
373 uint32_t start_time;
374
375 can->MCR &= ~CAN_MCR_INRQ;
376 start_time = k_cycle_get_32();
377
378 while ((can->MSR & CAN_MSR_INAK) != 0U) {
379 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
380 return -EAGAIN;
381 }
382 }
383
384 return 0;
385 }
386
can_stm32_leave_sleep_mode(CAN_TypeDef * can)387 static int can_stm32_leave_sleep_mode(CAN_TypeDef *can)
388 {
389 uint32_t start_time;
390
391 can->MCR &= ~CAN_MCR_SLEEP;
392 start_time = k_cycle_get_32();
393
394 while ((can->MSR & CAN_MSR_SLAK) != 0) {
395 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
396 return -EAGAIN;
397 }
398 }
399
400 return 0;
401 }
402
can_stm32_get_capabilities(const struct device * dev,can_mode_t * cap)403 static int can_stm32_get_capabilities(const struct device *dev, can_mode_t *cap)
404 {
405 ARG_UNUSED(dev);
406
407 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT;
408
409 return 0;
410 }
411
can_stm32_start(const struct device * dev)412 static int can_stm32_start(const struct device *dev)
413 {
414 const struct can_stm32_config *cfg = dev->config;
415 struct can_stm32_data *data = dev->data;
416 CAN_TypeDef *can = cfg->can;
417 int ret = 0;
418
419 k_mutex_lock(&data->inst_mutex, K_FOREVER);
420
421 if (data->started) {
422 ret = -EALREADY;
423 goto unlock;
424 }
425
426 if (cfg->phy != NULL) {
427 ret = can_transceiver_enable(cfg->phy);
428 if (ret != 0) {
429 LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
430 goto unlock;
431 }
432 }
433
434 CAN_STATS_RESET(dev);
435
436 ret = can_stm32_leave_init_mode(can);
437 if (ret < 0) {
438 LOG_ERR("Failed to leave init mode");
439
440 if (cfg->phy != NULL) {
441 /* Attempt to disable the CAN transceiver in case of error */
442 (void)can_transceiver_disable(cfg->phy);
443 }
444
445 ret = -EIO;
446 goto unlock;
447 }
448
449 data->started = true;
450
451 unlock:
452 k_mutex_unlock(&data->inst_mutex);
453
454 return ret;
455 }
456
can_stm32_stop(const struct device * dev)457 static int can_stm32_stop(const struct device *dev)
458 {
459 const struct can_stm32_config *cfg = dev->config;
460 struct can_stm32_data *data = dev->data;
461 CAN_TypeDef *can = cfg->can;
462 int ret = 0;
463
464 k_mutex_lock(&data->inst_mutex, K_FOREVER);
465
466 if (!data->started) {
467 ret = -EALREADY;
468 goto unlock;
469 }
470
471 ret = can_stm32_enter_init_mode(can);
472 if (ret < 0) {
473 LOG_ERR("Failed to enter init mode");
474 ret = -EIO;
475 goto unlock;
476 }
477
478 /* Abort any pending transmissions */
479 can_stm32_signal_tx_complete(dev, &data->mb0, -ENETDOWN);
480 can_stm32_signal_tx_complete(dev, &data->mb1, -ENETDOWN);
481 can_stm32_signal_tx_complete(dev, &data->mb2, -ENETDOWN);
482 can->TSR |= CAN_TSR_ABRQ2 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ0;
483
484 if (cfg->phy != NULL) {
485 ret = can_transceiver_disable(cfg->phy);
486 if (ret != 0) {
487 LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
488 goto unlock;
489 }
490 }
491
492 data->started = false;
493
494 unlock:
495 k_mutex_unlock(&data->inst_mutex);
496
497 return ret;
498 }
499
can_stm32_set_mode(const struct device * dev,can_mode_t mode)500 static int can_stm32_set_mode(const struct device *dev, can_mode_t mode)
501 {
502 const struct can_stm32_config *cfg = dev->config;
503 CAN_TypeDef *can = cfg->can;
504 struct can_stm32_data *data = dev->data;
505
506 LOG_DBG("Set mode %d", mode);
507
508 if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT)) != 0) {
509 LOG_ERR("unsupported mode: 0x%08x", mode);
510 return -ENOTSUP;
511 }
512
513 if (data->started) {
514 return -EBUSY;
515 }
516
517 k_mutex_lock(&data->inst_mutex, K_FOREVER);
518
519 if ((mode & CAN_MODE_LOOPBACK) != 0) {
520 /* Loopback mode */
521 can->BTR |= CAN_BTR_LBKM;
522 } else {
523 can->BTR &= ~CAN_BTR_LBKM;
524 }
525
526 if ((mode & CAN_MODE_LISTENONLY) != 0) {
527 /* Silent mode */
528 can->BTR |= CAN_BTR_SILM;
529 } else {
530 can->BTR &= ~CAN_BTR_SILM;
531 }
532
533 if ((mode & CAN_MODE_ONE_SHOT) != 0) {
534 /* No automatic retransmission */
535 can->MCR |= CAN_MCR_NART;
536 } else {
537 can->MCR &= ~CAN_MCR_NART;
538 }
539
540 k_mutex_unlock(&data->inst_mutex);
541
542 return 0;
543 }
544
can_stm32_set_timing(const struct device * dev,const struct can_timing * timing)545 static int can_stm32_set_timing(const struct device *dev,
546 const struct can_timing *timing)
547 {
548 const struct can_stm32_config *cfg = dev->config;
549 CAN_TypeDef *can = cfg->can;
550 struct can_stm32_data *data = dev->data;
551
552 k_mutex_lock(&data->inst_mutex, K_FOREVER);
553
554 if (data->started) {
555 k_mutex_unlock(&data->inst_mutex);
556 return -EBUSY;
557 }
558
559 can->BTR = (can->BTR & ~(CAN_BTR_SJW_Msk | CAN_BTR_BRP_Msk |
560 CAN_BTR_TS1_Msk | CAN_BTR_TS2_Msk)) |
561 (((timing->sjw - 1) << CAN_BTR_SJW_Pos) & CAN_BTR_SJW_Msk) |
562 (((timing->phase_seg1 - 1) << CAN_BTR_TS1_Pos) & CAN_BTR_TS1_Msk) |
563 (((timing->phase_seg2 - 1) << CAN_BTR_TS2_Pos) & CAN_BTR_TS2_Msk) |
564 (((timing->prescaler - 1) << CAN_BTR_BRP_Pos) & CAN_BTR_BRP_Msk);
565
566 k_mutex_unlock(&data->inst_mutex);
567
568 return 0;
569 }
570
can_stm32_get_core_clock(const struct device * dev,uint32_t * rate)571 static int can_stm32_get_core_clock(const struct device *dev, uint32_t *rate)
572 {
573 const struct can_stm32_config *cfg = dev->config;
574 const struct device *clock;
575 int ret;
576
577 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
578
579 ret = clock_control_get_rate(clock,
580 (clock_control_subsys_t) &cfg->pclken,
581 rate);
582 if (ret != 0) {
583 LOG_ERR("Failed call clock_control_get_rate: return [%d]", ret);
584 return -EIO;
585 }
586
587 return 0;
588 }
589
can_stm32_get_max_bitrate(const struct device * dev,uint32_t * max_bitrate)590 static int can_stm32_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate)
591 {
592 const struct can_stm32_config *config = dev->config;
593
594 *max_bitrate = config->max_bitrate;
595
596 return 0;
597 }
598
can_stm32_get_max_filters(const struct device * dev,bool ide)599 static int can_stm32_get_max_filters(const struct device *dev, bool ide)
600 {
601 ARG_UNUSED(dev);
602
603 if (ide) {
604 return CONFIG_CAN_MAX_EXT_ID_FILTER;
605 } else {
606 return CONFIG_CAN_MAX_STD_ID_FILTER;
607 }
608 }
609
can_stm32_init(const struct device * dev)610 static int can_stm32_init(const struct device *dev)
611 {
612 const struct can_stm32_config *cfg = dev->config;
613 struct can_stm32_data *data = dev->data;
614 CAN_TypeDef *can = cfg->can;
615 struct can_timing timing = { 0 };
616 const struct device *clock;
617 uint32_t bank_offset;
618 int ret;
619
620 k_mutex_init(&filter_mutex);
621 k_mutex_init(&data->inst_mutex);
622 k_sem_init(&data->tx_int_sem, 0, 1);
623
624 if (cfg->phy != NULL) {
625 if (!device_is_ready(cfg->phy)) {
626 LOG_ERR("CAN transceiver not ready");
627 return -ENODEV;
628 }
629 }
630
631 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
632 if (!device_is_ready(clock)) {
633 LOG_ERR("clock control device not ready");
634 return -ENODEV;
635 }
636
637 ret = clock_control_on(clock, (clock_control_subsys_t) &cfg->pclken);
638 if (ret != 0) {
639 LOG_ERR("HAL_CAN_Init clock control on failed: %d", ret);
640 return -EIO;
641 }
642
643 /* Configure dt provided device signals when available */
644 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
645 if (ret < 0) {
646 LOG_ERR("CAN pinctrl setup failed (%d)", ret);
647 return ret;
648 }
649
650 ret = can_stm32_leave_sleep_mode(can);
651 if (ret) {
652 LOG_ERR("Failed to exit sleep mode");
653 return ret;
654 }
655
656 ret = can_stm32_enter_init_mode(can);
657 if (ret) {
658 LOG_ERR("Failed to enter init mode");
659 return ret;
660 }
661
662 /* configure scale of filter banks < CONFIG_CAN_MAX_EXT_ID_FILTER for ext ids */
663 bank_offset = (cfg->can == cfg->master_can) ? 0 : CAN_STM32_NUM_FILTER_BANKS;
664 cfg->master_can->FMR |= CAN_FMR_FINIT;
665 cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1) << bank_offset;
666 cfg->master_can->FMR &= ~CAN_FMR_FINIT;
667
668 can->MCR &= ~CAN_MCR_TTCM & ~CAN_MCR_ABOM & ~CAN_MCR_AWUM &
669 ~CAN_MCR_NART & ~CAN_MCR_RFLM & ~CAN_MCR_TXFP;
670 #ifdef CONFIG_CAN_RX_TIMESTAMP
671 can->MCR |= CAN_MCR_TTCM;
672 #endif
673 #ifdef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
674 can->MCR |= CAN_MCR_ABOM;
675 #endif
676 if (cfg->sample_point && USE_SP_ALGO) {
677 ret = can_calc_timing(dev, &timing, cfg->bus_speed,
678 cfg->sample_point);
679 if (ret == -EINVAL) {
680 LOG_ERR("Can't find timing for given param");
681 return -EIO;
682 }
683 LOG_DBG("Presc: %d, TS1: %d, TS2: %d",
684 timing.prescaler, timing.phase_seg1, timing.phase_seg2);
685 LOG_DBG("Sample-point err : %d", ret);
686 } else {
687 timing.sjw = cfg->sjw;
688 timing.prop_seg = 0;
689 timing.phase_seg1 = cfg->prop_ts1;
690 timing.phase_seg2 = cfg->ts2;
691 ret = can_calc_prescaler(dev, &timing, cfg->bus_speed);
692 if (ret) {
693 LOG_WRN("Bitrate error: %d", ret);
694 }
695 }
696
697 ret = can_set_timing(dev, &timing);
698 if (ret) {
699 return ret;
700 }
701
702 ret = can_stm32_set_mode(dev, CAN_MODE_NORMAL);
703 if (ret) {
704 return ret;
705 }
706
707 (void)can_stm32_get_state(dev, &data->state, NULL);
708
709 cfg->config_irq(can);
710 can->IER |= CAN_IER_TMEIE;
711
712 return 0;
713 }
714
can_stm32_set_state_change_callback(const struct device * dev,can_state_change_callback_t cb,void * user_data)715 static void can_stm32_set_state_change_callback(const struct device *dev,
716 can_state_change_callback_t cb,
717 void *user_data)
718 {
719 struct can_stm32_data *data = dev->data;
720 const struct can_stm32_config *cfg = dev->config;
721 CAN_TypeDef *can = cfg->can;
722
723 data->state_change_cb = cb;
724 data->state_change_cb_data = user_data;
725
726 if (cb == NULL) {
727 can->IER &= ~(CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE);
728 } else {
729 can->IER |= CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE;
730 }
731 }
732
733 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
can_stm32_recover(const struct device * dev,k_timeout_t timeout)734 static int can_stm32_recover(const struct device *dev, k_timeout_t timeout)
735 {
736 const struct can_stm32_config *cfg = dev->config;
737 struct can_stm32_data *data = dev->data;
738 CAN_TypeDef *can = cfg->can;
739 int ret = -EAGAIN;
740 int64_t start_time;
741
742 if (!data->started) {
743 return -ENETDOWN;
744 }
745
746 if (!(can->ESR & CAN_ESR_BOFF)) {
747 return 0;
748 }
749
750 if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) {
751 return -EAGAIN;
752 }
753
754 ret = can_stm32_enter_init_mode(can);
755 if (ret) {
756 goto done;
757 }
758
759 can_stm32_leave_init_mode(can);
760
761 start_time = k_uptime_ticks();
762
763 while (can->ESR & CAN_ESR_BOFF) {
764 if (!K_TIMEOUT_EQ(timeout, K_FOREVER) &&
765 k_uptime_ticks() - start_time >= timeout.ticks) {
766 goto done;
767 }
768 }
769
770 ret = 0;
771
772 done:
773 k_mutex_unlock(&data->inst_mutex);
774 return ret;
775 }
776 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
777
778
can_stm32_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)779 static int can_stm32_send(const struct device *dev, const struct can_frame *frame,
780 k_timeout_t timeout, can_tx_callback_t callback,
781 void *user_data)
782 {
783 const struct can_stm32_config *cfg = dev->config;
784 struct can_stm32_data *data = dev->data;
785 CAN_TypeDef *can = cfg->can;
786 uint32_t transmit_status_register = can->TSR;
787 CAN_TxMailBox_TypeDef *mailbox = NULL;
788 struct can_stm32_mailbox *mb = NULL;
789
790 LOG_DBG("Sending %d bytes on %s. "
791 "Id: 0x%x, "
792 "ID type: %s, "
793 "Remote Frame: %s"
794 , frame->dlc, dev->name
795 , frame->id
796 , (frame->flags & CAN_FRAME_IDE) != 0 ? "extended" : "standard"
797 , (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no");
798
799 __ASSERT_NO_MSG(callback != NULL);
800 __ASSERT(frame->dlc == 0U || frame->data != NULL, "Dataptr is null");
801
802 if (frame->dlc > CAN_MAX_DLC) {
803 LOG_ERR("DLC of %d exceeds maximum (%d)", frame->dlc, CAN_MAX_DLC);
804 return -EINVAL;
805 }
806
807 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) {
808 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
809 return -ENOTSUP;
810 }
811
812 if (!data->started) {
813 return -ENETDOWN;
814 }
815
816 if (can->ESR & CAN_ESR_BOFF) {
817 return -ENETUNREACH;
818 }
819
820 k_mutex_lock(&data->inst_mutex, K_FOREVER);
821 while (!(transmit_status_register & CAN_TSR_TME)) {
822 k_mutex_unlock(&data->inst_mutex);
823 LOG_DBG("Transmit buffer full");
824 if (k_sem_take(&data->tx_int_sem, timeout)) {
825 return -EAGAIN;
826 }
827
828 k_mutex_lock(&data->inst_mutex, K_FOREVER);
829 transmit_status_register = can->TSR;
830 }
831
832 if (transmit_status_register & CAN_TSR_TME0) {
833 LOG_DBG("Using TX mailbox 0");
834 mailbox = &can->sTxMailBox[0];
835 mb = &(data->mb0);
836 } else if (transmit_status_register & CAN_TSR_TME1) {
837 LOG_DBG("Using TX mailbox 1");
838 mailbox = &can->sTxMailBox[1];
839 mb = &data->mb1;
840 } else if (transmit_status_register & CAN_TSR_TME2) {
841 LOG_DBG("Using TX mailbox 2");
842 mailbox = &can->sTxMailBox[2];
843 mb = &data->mb2;
844 }
845
846 mb->tx_callback = callback;
847 mb->callback_arg = user_data;
848
849 /* mailbox identifier register setup */
850 mailbox->TIR &= CAN_TI0R_TXRQ;
851
852 if ((frame->flags & CAN_FRAME_IDE) != 0) {
853 mailbox->TIR |= (frame->id << CAN_TI0R_EXID_Pos)
854 | CAN_TI0R_IDE;
855 } else {
856 mailbox->TIR |= (frame->id << CAN_TI0R_STID_Pos);
857 }
858
859 if ((frame->flags & CAN_FRAME_RTR) != 0) {
860 mailbox->TIR |= CAN_TI1R_RTR;
861 } else {
862 mailbox->TDLR = frame->data_32[0];
863 mailbox->TDHR = frame->data_32[1];
864 }
865
866 mailbox->TDTR = (mailbox->TDTR & ~CAN_TDT1R_DLC) |
867 ((frame->dlc & 0xF) << CAN_TDT1R_DLC_Pos);
868
869 mailbox->TIR |= CAN_TI0R_TXRQ;
870 k_mutex_unlock(&data->inst_mutex);
871
872 return 0;
873 }
874
can_stm32_set_filter_bank(int filter_id,CAN_FilterRegister_TypeDef * filter_reg,bool ide,uint32_t id,uint32_t mask)875 static void can_stm32_set_filter_bank(int filter_id, CAN_FilterRegister_TypeDef *filter_reg,
876 bool ide, uint32_t id, uint32_t mask)
877 {
878 if (ide) {
879 filter_reg->FR1 = id;
880 filter_reg->FR2 = mask;
881 } else {
882 if ((filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER) % 2 == 0) {
883 /* even std filter id: first 1/2 bank */
884 filter_reg->FR1 = id | (mask << 16);
885 } else {
886 /* uneven std filter id: first 1/2 bank */
887 filter_reg->FR2 = id | (mask << 16);
888 }
889 }
890 }
891
can_stm32_filter_to_std_mask(const struct can_filter * filter)892 static inline uint32_t can_stm32_filter_to_std_mask(const struct can_filter *filter)
893 {
894 uint32_t rtr_mask = (filter->flags & (CAN_FILTER_DATA | CAN_FILTER_RTR)) !=
895 (CAN_FILTER_DATA | CAN_FILTER_RTR) ? 1U : 0U;
896
897 return (filter->mask << CAN_STM32_FIRX_STD_ID_POS) |
898 (rtr_mask << CAN_STM32_FIRX_STD_RTR_POS) |
899 (1U << CAN_STM32_FIRX_STD_IDE_POS);
900 }
901
can_stm32_filter_to_ext_mask(const struct can_filter * filter)902 static inline uint32_t can_stm32_filter_to_ext_mask(const struct can_filter *filter)
903 {
904 uint32_t rtr_mask = (filter->flags & (CAN_FILTER_DATA | CAN_FILTER_RTR)) !=
905 (CAN_FILTER_DATA | CAN_FILTER_RTR) ? 1U : 0U;
906
907 return (filter->mask << CAN_STM32_FIRX_EXT_EXT_ID_POS) |
908 (rtr_mask << CAN_STM32_FIRX_EXT_RTR_POS) |
909 (1U << CAN_STM32_FIRX_EXT_IDE_POS);
910 }
911
can_stm32_filter_to_std_id(const struct can_filter * filter)912 static inline uint32_t can_stm32_filter_to_std_id(const struct can_filter *filter)
913 {
914 return (filter->id << CAN_STM32_FIRX_STD_ID_POS) |
915 (((filter->flags & CAN_FILTER_RTR) != 0) ? (1U << CAN_STM32_FIRX_STD_RTR_POS) : 0U);
916 }
917
can_stm32_filter_to_ext_id(const struct can_filter * filter)918 static inline uint32_t can_stm32_filter_to_ext_id(const struct can_filter *filter)
919 {
920 return (filter->id << CAN_STM32_FIRX_EXT_EXT_ID_POS) |
921 (((filter->flags & CAN_FILTER_RTR) != 0) ?
922 (1U << CAN_STM32_FIRX_EXT_RTR_POS) : 0U) |
923 (1U << CAN_STM32_FIRX_EXT_IDE_POS);
924 }
925
can_stm32_set_filter(const struct device * dev,const struct can_filter * filter)926 static inline int can_stm32_set_filter(const struct device *dev, const struct can_filter *filter)
927 {
928 const struct can_stm32_config *cfg = dev->config;
929 struct can_stm32_data *data = dev->data;
930 CAN_TypeDef *can = cfg->master_can;
931 uint32_t mask = 0U;
932 uint32_t id = 0U;
933 int filter_id = -ENOSPC;
934 int bank_offset = 0;
935 int bank_num;
936
937 if (cfg->can != cfg->master_can) {
938 /* CAN slave instance: start with offset */
939 bank_offset = CAN_STM32_NUM_FILTER_BANKS;
940 }
941
942 if ((filter->flags & CAN_FILTER_IDE) != 0) {
943 for (int i = 0; i < CONFIG_CAN_MAX_EXT_ID_FILTER; i++) {
944 if (data->rx_cb_ext[i] == NULL) {
945 id = can_stm32_filter_to_ext_id(filter);
946 mask = can_stm32_filter_to_ext_mask(filter);
947 filter_id = i;
948 bank_num = bank_offset + i;
949 break;
950 }
951 }
952 } else {
953 for (int i = 0; i < CONFIG_CAN_MAX_STD_ID_FILTER; i++) {
954 if (data->rx_cb_std[i] == NULL) {
955 id = can_stm32_filter_to_std_id(filter);
956 mask = can_stm32_filter_to_std_mask(filter);
957 filter_id = CONFIG_CAN_MAX_EXT_ID_FILTER + i;
958 bank_num = bank_offset + CONFIG_CAN_MAX_EXT_ID_FILTER + i / 2;
959 break;
960 }
961 }
962 }
963
964 if (filter_id != -ENOSPC) {
965 LOG_DBG("Adding filter_id %d, CAN ID: 0x%x, mask: 0x%x",
966 filter_id, filter->id, filter->mask);
967
968 /* set the filter init mode */
969 can->FMR |= CAN_FMR_FINIT;
970
971 can_stm32_set_filter_bank(filter_id, &can->sFilterRegister[bank_num],
972 (filter->flags & CAN_FILTER_IDE) != 0,
973 id, mask);
974
975 can->FA1R |= 1U << bank_num;
976 can->FMR &= ~(CAN_FMR_FINIT);
977 } else {
978 LOG_WRN("No free filter left");
979 }
980
981 return filter_id;
982 }
983
984
985 /*
986 * This driver uses masked mode for all filters (CAN_FM1R left at reset value
987 * 0x00) in order to simplify mapping between filter match index from the FIFOs
988 * and array index for the callbacks. All ext ID filters are stored in the
989 * banks below CONFIG_CAN_MAX_EXT_ID_FILTER, followed by the std ID filters,
990 * which consume only 1/2 bank per filter.
991 *
992 * The more complicated list mode must be implemented if someone requires more
993 * than 28 std ID or 14 ext ID filters.
994 *
995 * Currently, all filter banks are assigned to FIFO 0 and FIFO 1 is not used.
996 */
can_stm32_add_rx_filter(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)997 static int can_stm32_add_rx_filter(const struct device *dev, can_rx_callback_t cb,
998 void *cb_arg, const struct can_filter *filter)
999 {
1000 struct can_stm32_data *data = dev->data;
1001 int filter_id;
1002
1003 if ((filter->flags & ~(CAN_FILTER_IDE | CAN_FILTER_DATA | CAN_FILTER_RTR)) != 0) {
1004 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
1005 return -ENOTSUP;
1006 }
1007
1008 k_mutex_lock(&filter_mutex, K_FOREVER);
1009 k_mutex_lock(&data->inst_mutex, K_FOREVER);
1010
1011 filter_id = can_stm32_set_filter(dev, filter);
1012 if (filter_id >= 0) {
1013 if ((filter->flags & CAN_FILTER_IDE) != 0) {
1014 data->rx_cb_ext[filter_id] = cb;
1015 data->cb_arg_ext[filter_id] = cb_arg;
1016 } else {
1017 data->rx_cb_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb;
1018 data->cb_arg_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb_arg;
1019 }
1020 }
1021
1022 k_mutex_unlock(&data->inst_mutex);
1023 k_mutex_unlock(&filter_mutex);
1024
1025 return filter_id;
1026 }
1027
can_stm32_remove_rx_filter(const struct device * dev,int filter_id)1028 static void can_stm32_remove_rx_filter(const struct device *dev, int filter_id)
1029 {
1030 const struct can_stm32_config *cfg = dev->config;
1031 struct can_stm32_data *data = dev->data;
1032 CAN_TypeDef *can = cfg->master_can;
1033 bool ide;
1034 int bank_offset = 0;
1035 int bank_num;
1036 bool bank_unused;
1037
1038 __ASSERT_NO_MSG(filter_id >= 0 && filter_id < CAN_STM32_MAX_FILTER_ID);
1039
1040 k_mutex_lock(&filter_mutex, K_FOREVER);
1041 k_mutex_lock(&data->inst_mutex, K_FOREVER);
1042
1043 if (cfg->can != cfg->master_can) {
1044 bank_offset = CAN_STM32_NUM_FILTER_BANKS;
1045 }
1046
1047 if (filter_id < CONFIG_CAN_MAX_EXT_ID_FILTER) {
1048 ide = true;
1049 bank_num = bank_offset + filter_id;
1050
1051 data->rx_cb_ext[filter_id] = NULL;
1052 data->cb_arg_ext[filter_id] = NULL;
1053
1054 bank_unused = true;
1055 } else {
1056 int filter_index = filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER;
1057
1058 ide = false;
1059 bank_num = bank_offset + CONFIG_CAN_MAX_EXT_ID_FILTER +
1060 (filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER) / 2;
1061
1062 data->rx_cb_std[filter_index] = NULL;
1063 data->cb_arg_std[filter_index] = NULL;
1064
1065 if (filter_index % 2 == 1) {
1066 bank_unused = data->rx_cb_std[filter_index - 1] == NULL;
1067 } else if (filter_index + 1 < CONFIG_CAN_MAX_STD_ID_FILTER) {
1068 bank_unused = data->rx_cb_std[filter_index + 1] == NULL;
1069 } else {
1070 bank_unused = true;
1071 }
1072 }
1073
1074 LOG_DBG("Removing filter_id %d, ide %d", filter_id, ide);
1075
1076 can->FMR |= CAN_FMR_FINIT;
1077
1078 can_stm32_set_filter_bank(filter_id, &can->sFilterRegister[bank_num],
1079 ide, 0, 0xFFFFFFFF);
1080
1081 if (bank_unused) {
1082 can->FA1R &= ~(1U << bank_num);
1083 LOG_DBG("Filter bank %d is unused -> deactivate", bank_num);
1084 }
1085
1086 can->FMR &= ~(CAN_FMR_FINIT);
1087
1088 k_mutex_unlock(&data->inst_mutex);
1089 k_mutex_unlock(&filter_mutex);
1090 }
1091
1092 static const struct can_driver_api can_api_funcs = {
1093 .get_capabilities = can_stm32_get_capabilities,
1094 .start = can_stm32_start,
1095 .stop = can_stm32_stop,
1096 .set_mode = can_stm32_set_mode,
1097 .set_timing = can_stm32_set_timing,
1098 .send = can_stm32_send,
1099 .add_rx_filter = can_stm32_add_rx_filter,
1100 .remove_rx_filter = can_stm32_remove_rx_filter,
1101 .get_state = can_stm32_get_state,
1102 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
1103 .recover = can_stm32_recover,
1104 #endif
1105 .set_state_change_callback = can_stm32_set_state_change_callback,
1106 .get_core_clock = can_stm32_get_core_clock,
1107 .get_max_bitrate = can_stm32_get_max_bitrate,
1108 .get_max_filters = can_stm32_get_max_filters,
1109 .timing_min = {
1110 .sjw = 0x1,
1111 .prop_seg = 0x00,
1112 .phase_seg1 = 0x01,
1113 .phase_seg2 = 0x01,
1114 .prescaler = 0x01
1115 },
1116 .timing_max = {
1117 .sjw = 0x04,
1118 .prop_seg = 0x00,
1119 .phase_seg1 = 0x10,
1120 .phase_seg2 = 0x08,
1121 .prescaler = 0x400
1122 }
1123 };
1124
1125 #ifdef CONFIG_SOC_SERIES_STM32F0X
1126 #define CAN_STM32_IRQ_INST(inst) \
1127 static void config_can_##inst##_irq(CAN_TypeDef *can) \
1128 { \
1129 IRQ_CONNECT(DT_INST_IRQN(inst), \
1130 DT_INST_IRQ(inst, priority), \
1131 can_stm32_isr, DEVICE_DT_INST_GET(inst), 0); \
1132 irq_enable(DT_INST_IRQN(inst)); \
1133 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1134 CAN_IER_FMPIE1 | CAN_IER_BOFIE; \
1135 if (IS_ENABLED(CONFIG_CAN_STATS)) { \
1136 can->IER |= CAN_IER_LECIE; \
1137 } \
1138 }
1139 #else
1140 #define CAN_STM32_IRQ_INST(inst) \
1141 static void config_can_##inst##_irq(CAN_TypeDef *can) \
1142 { \
1143 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, rx0, irq), \
1144 DT_INST_IRQ_BY_NAME(inst, rx0, priority), \
1145 can_stm32_rx_isr, DEVICE_DT_INST_GET(inst), 0); \
1146 irq_enable(DT_INST_IRQ_BY_NAME(inst, rx0, irq)); \
1147 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, tx, irq), \
1148 DT_INST_IRQ_BY_NAME(inst, tx, priority), \
1149 can_stm32_tx_isr, DEVICE_DT_INST_GET(inst), 0); \
1150 irq_enable(DT_INST_IRQ_BY_NAME(inst, tx, irq)); \
1151 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, sce, irq), \
1152 DT_INST_IRQ_BY_NAME(inst, sce, priority), \
1153 can_stm32_state_change_isr, \
1154 DEVICE_DT_INST_GET(inst), 0); \
1155 irq_enable(DT_INST_IRQ_BY_NAME(inst, sce, irq)); \
1156 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1157 CAN_IER_FMPIE1 | CAN_IER_BOFIE; \
1158 if (IS_ENABLED(CONFIG_CAN_STATS)) { \
1159 can->IER |= CAN_IER_LECIE; \
1160 } \
1161 }
1162 #endif /* CONFIG_SOC_SERIES_STM32F0X */
1163
1164 #define CAN_STM32_CONFIG_INST(inst) \
1165 PINCTRL_DT_INST_DEFINE(inst); \
1166 static const struct can_stm32_config can_stm32_cfg_##inst = { \
1167 .can = (CAN_TypeDef *)DT_INST_REG_ADDR(inst), \
1168 .master_can = (CAN_TypeDef *)DT_INST_PROP_OR(inst, \
1169 master_can_reg, DT_INST_REG_ADDR(inst)), \
1170 .bus_speed = DT_INST_PROP(inst, bus_speed), \
1171 .sample_point = DT_INST_PROP_OR(inst, sample_point, 0), \
1172 .sjw = DT_INST_PROP_OR(inst, sjw, 1), \
1173 .prop_ts1 = DT_INST_PROP_OR(inst, prop_seg, 0) + \
1174 DT_INST_PROP_OR(inst, phase_seg1, 0), \
1175 .ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
1176 .pclken = { \
1177 .enr = DT_INST_CLOCKS_CELL(inst, bits), \
1178 .bus = DT_INST_CLOCKS_CELL(inst, bus), \
1179 }, \
1180 .config_irq = config_can_##inst##_irq, \
1181 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1182 .phy = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(inst, phys)), \
1183 .max_bitrate = DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(inst, 1000000), \
1184 };
1185
1186 #define CAN_STM32_DATA_INST(inst) \
1187 static struct can_stm32_data can_stm32_dev_data_##inst;
1188
1189 #define CAN_STM32_DEFINE_INST(inst) \
1190 CAN_DEVICE_DT_INST_DEFINE(inst, can_stm32_init, NULL, \
1191 &can_stm32_dev_data_##inst, &can_stm32_cfg_##inst, \
1192 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
1193 &can_api_funcs);
1194
1195 #define CAN_STM32_INST(inst) \
1196 CAN_STM32_IRQ_INST(inst) \
1197 CAN_STM32_CONFIG_INST(inst) \
1198 CAN_STM32_DATA_INST(inst) \
1199 CAN_STM32_DEFINE_INST(inst)
1200
1201 DT_INST_FOREACH_STATUS_OKAY(CAN_STM32_INST)
1202
