1/*
2 * Copyright (c) 2018 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <mem.h>
10
11#define DT_DRAM_SIZE		DT_SIZE_M(2048)
12
13#include <intel/apollo_lake.dtsi>
14
15/ {
16	model = "up_squared";
17	compatible = "up_board,up_squared";
18
19	aliases {
20		i2c-0 = &i2c0;
21		i2c-1 = &i2c1;
22	};
23
24	chosen {
25		zephyr,sram = &dram0;
26		zephyr,console = &uart0;
27		zephyr,shell-uart = &uart0;
28		zephyr,bt-uart = &uart1;
29		zephyr,uart-pipe = &uart1;
30		zephyr,bt-mon-uart = &uart1;
31	};
32
33	cpus {
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		cpu@0 {
38			device_type = "cpu";
39			compatible = "intel,apollo-lake";
40			d-cache-line-size = <64>;
41			reg = <0>;
42		};
43
44		cpu@1 {
45			device_type = "cpu";
46			compatible = "intel,apollo-lake";
47			d-cache-line-size = <64>;
48			reg = <1>;
49		};
50	};
51};
52
53&hpet {
54	status = "disabled";
55};
56