1.. _qemu_nios2:
2
3Altera Nios-II Emulation (QEMU)
4###############################
5
6Overview
7********
8
9This board configuration will use QEMU to emulate the Altera MAX 10 platform.
10
11This configuration provides support for an Altera Nios-II CPU and these devices:
12
13* Internal Interrupt Controller
14* Altera Avalon Timer
15* NS16550 UART
16
17.. note::
18   This board configuration makes no claims about its suitability for use
19   with an actual ti_lm3s6965 hardware system, or any other hardware system.
20
21Hardware
22********
23Supported Features
24==================
25
26The following hardware features are supported:
27
28+--------------+------------+----------------------+
29| Interface    | Controller | Driver/Component     |
30+==============+============+======================+
31| IIC          | on-chip    | Internal interrupt   |
32|              |            | controller           |
33+--------------+------------+----------------------+
34| NS16550      | on-chip    | serial port          |
35| UART         |            |                      |
36+--------------+------------+----------------------+
37| TIMER        | on-chip    | system clock         |
38+--------------+------------+----------------------+
39
40The kernel currently does not support other hardware features on this platform.
41
42Devices
43========
44System Clock
45------------
46
47This board configuration uses a system clock frequency of 50 MHz.
48
49Serial Port
50-----------
51
52This board configuration uses a single serial communication channel with the
53CPU's UART0.
54
55If SLIP networking is enabled (see below), an additional serial port will be
56used for it.
57
58Known Problems or Limitations
59==============================
60
61The following platform features are unsupported:
62
63* Memory protection through optional MPU.  However, using a XIP kernel
64  effectively provides TEXT/RODATA write protection in ROM.
65* Writing to the hardware's flash memory
66* Serial port in Direct Memory Access (DMA) mode
67* Serial Peripheral Interface (SPI) flash
68* General-Purpose Input/Output (GPIO)
69* Inter-Integrated Circuit (I2C)
70* Ethernet
71
72
73Programming and Debugging
74*************************
75
76Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
77emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
78
79.. zephyr-app-commands::
80   :zephyr-app: samples/synchronization
81   :host-os: unix
82   :board: qemu_nios2
83   :goals: run
84
85This will build an image with the synchronization sample app, boot it using
86QEMU, and display the following console output:
87
88.. code-block:: console
89
90        ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
91        threadA: Hello World from arm!
92        threadB: Hello World from arm!
93        threadA: Hello World from arm!
94        threadB: Hello World from arm!
95        threadA: Hello World from arm!
96        threadB: Hello World from arm!
97        threadA: Hello World from arm!
98        threadB: Hello World from arm!
99        threadA: Hello World from arm!
100        threadB: Hello World from arm!
101
102Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
103
104Debugging
105=========
106
107Refer to the detailed overview about :ref:`application_debugging`.
108
109Networking
110==========
111
112The board supports SLIP networking over an emulated serial port
113(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
114:ref:`networking_with_qemu`.
115
116References
117**********
118
119* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
120* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
121* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
122* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
123* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
124* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
125* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
126
127
128.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite
129