1.. _nxp_ls1046ardb:
2
3NXP LS1046A RDB
4#################################
5
6Overview
7********
8
9The LS1046A reference design board (RDB) is a high-performance computing,
10evaluation, and development platform that supports the Layerscape LS1046A
11architecture processor. The LS1046ARDB board supports the Layerscape LS1046A
12processor and is optimized to support the DDR4 memory and a full complement
13of high-speed SerDes ports.
14
15The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
16cores with packet processing acceleration and high-speed peripherals. The
17impressive performance of more than 32,000 CoreMarks, paired with 10 Gb
18Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an
19excellent combination for a range of enterprise and service provider
20networking, storage, security and industrial applications.
21
22Hardware
23********
24
25LS1046A RDB boards supports the following features:
26
27
28- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
29- Supports 8 GB DDR4 SDRAM memory
30- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
31  memory device
32- One 512 MB SLC NAND flash with ECC support (1.8 V)
33- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
34- Support two 64 MB onboard QSPI NOR flash memories
35- USB:
36  - Two USB 3.0 controllers with integrated PHYs.
37  - One USB1 3.0 port is connected to a Type A host connector.
38  - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector.
39  - One USB2.0 is connected to miniPCIe connector .
40- Ethernet:
41  - Supports SGMII 1G PHYs at Lane 2 and Lane 3
42  - Supports SFP+module with XFI retimers
43  - Supports AQR106/107 10G PHY with XFI/2.5G SGMII
44- PCIe and SATA:
45  - Mini PCIe express x1 (Gen1/2/3)card
46  - Standard PCIe x1 (Gen1/2/3) card
47  - Standard PCIe x1 (Gen1/2/3) card
48  - One SATA 3.0 connector
49
50Supported Features
51==================
52
53NXP LS1046A RDB board default configuration supports the following
54hardware features:
55
56+-----------+------------+--------------------------------------+
57| Interface | Controller | Driver/Component                     |
58+===========+============+======================================+
59| GIC-400   | on-chip    | GICv2 interrupt controller           |
60+-----------+------------+--------------------------------------+
61| ARM TIMER | on-chip    | System Clock                         |
62+-----------+------------+--------------------------------------+
63| UART      | on-chip    | NS16550 compatible serial port       |
64+-----------+------------+--------------------------------------+
65
66Other hardware features have not been enabled yet for this board.
67
68The default configuration can be found in the defconfig file for NON-SMP:
69
70        ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig``
71
72Or for SMP running on all four CPU Cores:
73
74	``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig``
75
76Or for SMP running on 2 CPU Cores (Core2 and Core3):
77
78	``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig``
79
80There are two serial port on the board: uart1 and uart2, Zephyr is using
81uart2 as serial console.
82
83Programming and Debugging
84*************************
85
86Use the following configuration to run basic Zephyr applications and
87kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample:
88
891. Non-SMP mode
90
91.. zephyr-app-commands::
92   :zephyr-app: samples/synchronization
93   :host-os: unix
94   :board: nxp_ls1046ardb
95   :goals: build
96
97This will build an image with the synchronization sample app.
98
99Use u-boot to load and kick Zephyr.bin to CPU Core0:
100
101.. code-block:: console
102
103	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go  0xc0000000;
104
105Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3:
106
107.. code-block:: console
108
109	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000;
110
111
112It will display the following console output:
113
114.. code-block:: console
115
116	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
117	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
118	thread_b: Hello World from cpu 0 on nxp_ls1046ardb!
119	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
120
1212. SMP mode running on 4 CPU Cores
122
123.. zephyr-app-commands::
124   :zephyr-app: samples/synchronization
125   :host-os: unix
126   :board: nxp_ls1046ardb_smp_4cores
127   :goals: build
128
129This will build an image with the synchronization sample app.
130
131Use u-boot to load and kick Zephyr.bin to CPU Core0:
132
133.. code-block:: console
134
135	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go  0xc0000000;
136
137It will display the following console output:
138
139.. code-block:: console
140
141	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
142	Secondary CPU core 1 (MPID:0x1) is up
143	Secondary CPU core 2 (MPID:0x2) is up
144	Secondary CPU core 3 (MPID:0x3) is up
145	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
146	thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
147	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
148
1493. SMP mode running on 2 CPU Cores: Core2 and Core3
150
151.. zephyr-app-commands::
152   :zephyr-app: samples/synchronization
153   :host-os: unix
154   :board: nxp_ls1046ardb_smp_2cores
155   :goals: build
156
157This will build an image with the synchronization sample app.
158
159Use u-boot to load and kick Zephyr.bin to CPU Core2:
160
161.. code-block:: console
162
163	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000;
164
165It will display the following console output:
166
167.. code-block:: console
168
169	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
170	Secondary CPU core 1 (MPID:0x3) is up
171	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
172	thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
173	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
174
1754. Running Zephyr on Jailhouse inmate Cell
176
177Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse
178inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3
179for Zephyr SMP 2cores image.
180
1811) Use root Cell dts to boot root Cell Linux.
182
1832) Install Jailhouse module:
184
185.. code-block:: console
186
187	modprobe jailhouse
188
1893) Run Zephyr demo in inmate Cell:
190
191.. code-block:: console
192
193	jailhouse enable ls1046a-rdb.cell
194	jailhouse cell create ls1046a-rdb-inmate-demo.cell
195	jailhouse cell load 1 zephyr.bin --address 0xc0000000
196	jailhouse cell start 1
197
198Flashing
199========
200
201Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card,
202EMMC, QSPI Flash or downloaded from network in uboot.
203
204Debugging
205=========
206
207LS1046A RDB board includes one JTAG connector on board, connect it to
208CodeWarrior TAP for debugging.
209
210References
211==========
212
213`Layerscape LS1046A Reference Design Board <https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB>`_
214
215`LS1046A Reference Manual <https://www.nxp.com/webapp/Download?colCode=LS1046ARM>`_
216