1.. _intel_socfpga_agilex5_socdk:
2
3Intel® Agilex™ 5 SoC FPGA Development Kit
4#########################################
5
6Overview
7********
8
9The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design
10environment that includes both hardware and software for developing
11Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for
12developing custom ARM* processor-based SoC designs and ideal for intelligent
13applications at the edge, embedded and more.
14
15Hardware
16********
17
18The Intel® Agilex™ 5 Development Kit supports the following physical features:
19
20- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with
21  multi-core ARM processors of Dual-core A55 and Dual-core A76
22- On-board 8 GB DDR5 memory
23- On-board JTAG Intel FPGA Download Cable II
24- QSPI flash daughtercard
25
26Supported Features
27==================
28The Intel® Agilex™ 5 SoC Development Kit configuration supports the following
29hardware features:
30
31+-----------+------------+---------------------------------------------+
32| Interface | Controller | Hardware Subsystem Vendor                   |
33+===========+============+=============================================+
34| GIC-600   | on-chip    | ARM GICv3 interrupt controller              |
35+-----------+------------+---------------------------------------------+
36| UART      | on-chip    | Synopsys Designware,NS16550 compatible      |
37+-----------+------------+---------------------------------------------+
38| ARM TIMER | on-chip    | ARM system timer                            |
39+-----------+------------+---------------------------------------------+
40| Reset     | on-chip    | Intel Corporation, SoCFPGA Reset controller |
41+-----------+------------+---------------------------------------------+
42| Clock     | on-chip    | Intel Corporation, SoCFPGA Clock controller |
43+-----------+------------+---------------------------------------------+
44
45NOTE: TODO, more details on dev kit will be updated as and when available.
46
47The default configuration can be found in the defconfig file:
48        `boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig`
49
50Programming and Debugging
51*************************
52
53Zephyr Boot Flow
54****************
55Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF).
56ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which
57provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface).
58
59Boot flow:
60        ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1)
61
62Intel Arm Trusted Firmware (ATF) can be downloaded from github:
63        `altera-opensource/arm-trusted-firmware <https://github.com/altera-opensource/arm-trusted-firmware.git>`_
64
65Flashing
66========
67Zephyr image can be loaded in DDR memory at address 0x80000000 from
68SD Card or QSPI Flash or NAND in ATF BL2.
69
70Debugging
71=========
72The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on
73board, connect it to Intel USB blaster download cables for debugging.
74
75Zephyr applications running on the Cortex-A55/A76 core can be tested by
76observing UART console output.
77
78References
79==========
80`Intel® Agilex™ 5 FPGA and SoC FPGA <https://www.intel.in/content/www/in/en/products/details/fpga/agilex/5.html>`_
81