1/*
2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h7b3Xi.dtsi>
9#include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "arduino_r3_connector.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "STMicroelectronics STM32H7B3I DISCOVERY KIT board";
16	compatible = "st,stm32h7b3i-dk";
17
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,display = &ltdc;
24		zephyr,canbus = &fdcan1;
25	};
26
27	leds {
28		compatible = "gpio-leds";
29		red_led: led_0 {
30			gpios = <&gpiog 11 GPIO_ACTIVE_HIGH>;
31			label = "User LD1";
32		};
33		blue_led: led_1 {
34			gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
35			label = "User LD2";
36		};
37	};
38
39	gpio_keys {
40		compatible = "gpio-keys";
41		user_button: button {
42			label = "User PB";
43			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
44			zephyr,code = <INPUT_KEY_0>;
45		};
46	};
47
48	lvgl_pointer {
49		compatible = "zephyr,lvgl-pointer-input";
50		input = <&ft5336>;
51	};
52
53	sdram2: sdram@d0000000 {
54		compatible = "zephyr,memory-region", "mmio-sram";
55		device_type = "memory";
56		reg = <0xd0000000 DT_SIZE_M(16)>;
57		zephyr,memory-region = "SDRAM2";
58		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
59	};
60
61	transceiver0: can-phy0 {
62		compatible = "microchip,mcp2562fd", "can-transceiver-gpio";
63		standby-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>;
64		max-bitrate = <5000000>;
65		#phy-cells = <0>;
66	};
67
68	aliases {
69		led0 = &blue_led;
70		led1 = &red_led;
71		sw0 = &user_button;
72		spi-flash0 = &mx25lm51245;
73	};
74};
75
76&clk_hsi48 {
77	status = "okay";
78};
79
80&clk_hse {
81	clock-frequency = <DT_FREQ_M(24)>;
82	status = "okay";
83};
84
85/* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
86&pll {
87	div-m = <12>;
88	mul-n = <280>;
89	div-p = <2>;
90	div-q = <7>;
91	div-r = <2>;
92	clocks = <&clk_hse>;
93	status = "okay";
94};
95
96/* PLL3R is used for outputting 9 MHz pixel clock for LTDC */
97&pll3 {
98	div-m = <8>;
99	mul-n = <60>;
100	div-p = <2>;
101	div-q = <2>;
102	div-r = <20>;
103	clocks = <&clk_hse>;
104	status = "okay";
105};
106
107&rcc {
108	clocks = <&pll>;
109	clock-frequency = <DT_FREQ_M(280)>;
110	d1cpre = <1>;
111	hpre = <1>;
112	d1ppre = <2>;
113	d2ppre1 = <2>;
114	d2ppre2 = <2>;
115	d3ppre = <2>;
116};
117
118&usart1 {
119	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
120	pinctrl-names = "default";
121	current-speed = <115200>;
122	status = "okay";
123};
124
125&uart4 {
126	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
127	pinctrl-names = "default";
128	current-speed = <115200>;
129	status = "okay";
130};
131
132&i2c4 {
133	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
134	pinctrl-names = "default";
135	clock-frequency = <I2C_BITRATE_FAST>;
136	status = "okay";
137
138	ft5336: ft5336@38 {
139		compatible = "focaltech,ft5336";
140		reg = <0x38>;
141		int-gpios = <&gpioh 2 0>;
142	};
143};
144
145&spi2 {
146	pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15 &spi2_nss_pi0>;
147	pinctrl-names = "default";
148	status = "okay";
149};
150
151/* Connect solder bridges SB3, SB4 and SB5 to use CAN connector (CN21) */
152&fdcan1 {
153	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
154	pinctrl-names = "default";
155	phys = <&transceiver0>;
156	bus-speed = <125000>;
157	bus-speed-data = <1000000>;
158	sample-point = <875>;
159	sample-point-data = <875>;
160	status = "okay";
161};
162
163&fmc {
164	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
165		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
166		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
167		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
168		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
169		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
170		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
171		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
172		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
173		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
174		     &fmc_d15_pd10>;
175	pinctrl-names = "default";
176	status = "okay";
177
178	sdram {
179		status = "okay";
180		power-up-delay = <100>;
181		num-auto-refresh = <8>;
182		mode-register = <0x220>;
183		refresh-rate = <0x603>;
184		bank@1 {
185			reg = <1>;
186			st,sdram-control = <STM32_FMC_SDRAM_NC_9
187						STM32_FMC_SDRAM_NR_12
188						STM32_FMC_SDRAM_MWID_16
189						STM32_FMC_SDRAM_NB_4
190						STM32_FMC_SDRAM_CAS_2
191						STM32_FMC_SDRAM_SDCLK_PERIOD_3
192						STM32_FMC_SDRAM_RBURST_ENABLE
193						STM32_FMC_SDRAM_RPIPE_2>;
194			st,sdram-timing = <2 7 4 7 2 2 2>;
195		};
196	};
197};
198
199&sdmmc1 {
200	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
201		     &sdmmc1_d2_pc10 &sdmmc1_d3_pc11
202		     &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
203	pinctrl-names = "default";
204	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
205	status = "okay";
206};
207
208&ltdc {
209	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
210		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
211		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
212		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
213		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
214		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
215		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi12 &ltdc_vsync_pi13>;
216	pinctrl-names = "default";
217	disp-on-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
218	bl-ctrl-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
219	ext-sdram = <&sdram2>;
220	status = "okay";
221
222	width = <480>;
223	height = <272>;
224	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
225	display-timings {
226		compatible = "zephyr,panel-timing";
227		de-active = <0>;
228		pixelclk-active = <0>;
229		hsync-active = <0>;
230		vsync-active = <0>;
231		hsync-len = <1>;
232		vsync-len = <10>;
233		hback-porch = <43>;
234		vback-porch = <12>;
235		hfront-porch = <8>;
236		vfront-porch = <4>;
237	};
238	def-back-color-red = <0xFF>;
239	def-back-color-green = <0xFF>;
240	def-back-color-blue = <0xFF>;
241};
242
243&octospi1 {
244	pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pg6
245		     &octospim_p1_io0_pd11 &octospim_p1_io1_pf9
246		     &octospim_p1_io2_pf7 &octospim_p1_io3_pf6
247		     &octospim_p1_io4_pc1 &octospim_p1_io5_ph3
248		     &octospim_p1_io6_pg9 &octospim_p1_io7_pd7
249		     &octospim_p1_dqs_pc5>;
250	pinctrl-names = "default";
251
252	status = "okay";
253
254	mx25lm51245: ospi-nor-flash@0 {
255		compatible = "st,stm32-ospi-nor";
256		reg = <0>;
257		ospi-max-frequency = <DT_FREQ_M(50)>;
258		size = <DT_SIZE_M(512)>; /* 512 Megabits */
259		spi-bus-width = <OSPI_OPI_MODE>;
260		data-rate = <OSPI_DTR_TRANSFER>;
261		status = "okay";
262		sfdp-bfp = [
263			53 46 44 50 06 01 02 ff
264			00 06 01 10 30 00 00 ff
265			C2 00 01 04 10 01 00 ff
266			84 00 01 02 C0 00 00 ff
267			00 00 00 00
268		];
269
270		partitions {
271			   compatible = "fixed-partitions";
272			   #address-cells = <1>;
273			   #size-cells = <1>;
274
275			   partition@0 {
276			       label = "nor";
277			       reg = <0x00000000 DT_SIZE_M(4)>;
278			   };
279		};
280	};
281};
282