1.. _scobc_module1:
2
3Space Cubics OBC module 1
4#########################
5
6Overview
7********
8
9`Space Cubics`_ OBC module 1 is a single board computer for spacecraft,
10especially for 3U CubeSats.  The board is based on Xilinx Artix-7 FPGA and
11implements ARM Cortex M3 as the main CPU.
12
13.. figure:: scobc.jpg
14   :align: center
15   :alt: Space Cubics OBC module 1
16
17   Space Cubics OBC module 1
18
19It is designed to survive in the severe space environment, extreme temperature,
20vacuum, and space radiation.
21
22As the name suggests, the board form factor is a module and requires a base I/O
23board connected at CON1, a board-to-board connector.  This modularity allows
24CubeSat designers the freedom to connect and expand the capability required for
25their mission.
26
27Hardware
28********
29
30Supported Features
31==================
32
33The Space Cubics OBC module 1 provides the following hardware features:
34
35+-----------+------------+------------------------------------+
36| Interface | Controller | Driver/Component                   |
37+===========+============+====================================+
38| NVIC      | on-chip    | nested vector interrupt controller |
39+-----------+------------+------------------------------------+
40| SYSTICK   | on-chip    | systick                            |
41+-----------+------------+------------------------------------+
42| UART      | on-chip    | serial port-polling;               |
43|           |            | serial port-interrupt              |
44+-----------+------------+------------------------------------+
45
46The default configuration for the board can be found in the defconfig file:
47:file:`boards/arm/scobc_module1/scobc_module1_defconfig`.
48
49Other hardware features are not currently supported by the port.
50
51System Clock
52============
53
54The board has two 24 MHz external oscillators connected to the FPGA for
55redundancy. The FPGA will select an active oscillator as CPU system clock.  The
56selected clock signal is then used by the CMT in the FPGA, and drives the CPU at
5748 MHz by default.
58
59Serial Port
60===========
61
62The default configuration contains one SC UART IP, which is register compatible
63with Xilinx UART Lite for basic TX and RX. This UART is configured as the
64default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx,
65respectively.
66
67Programming and Debugging
68*************************
69
70Flashing
71========
72
73Here is an example for building and flashing the \`hello\_world\`
74application for the board:
75
76Here is an example for building and flashing the :ref:`hello_world` application
77for the default design:
78
79.. zephyr-app-commands::
80   :zephyr-app: samples/hello_world
81   :board: scobc_module1
82   :goals: flash
83
84After flashing, you should see message similar to the following in the terminal:
85
86.. code-block:: console
87
88   *** Booting Zephyr OS build zephyr-v2.7.99  ***
89   Hello World! scobc_module1
90
91Note, however, that the application was not persisted in flash memory by the
92above steps. It was merely written to internal RAM in the FPGA.
93
94Debugging
95=========
96
97Here is an example for the :ref:`hello_world` application.
98
99.. zephyr-app-commands::
100   :zephyr-app: samples/hello_world
101   :board: scobc_module1
102   :goals: debug
103
104Step through the application in your debugger, and you should see a message
105similar to the following in the terminal:
106
107.. code-block:: console
108
109   *** Booting Zephyr OS build zephyr-v2.7.99  ***
110   Hello World! scobc_module1
111
112References
113**********
114
115.. target-notes::
116
117.. _Space Cubics:
118   https://spacecubics.com/
119