1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 7)>,
12				<NRF_PSEL(UART_CTS, 0, 11)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 7)>,
21				<NRF_PSEL(UART_CTS, 0, 11)>;
22			low-power-enable;
23		};
24	};
25
26	uart1_default: uart1_default {
27		group1 {
28			psels = <NRF_PSEL(UART_TX, 1, 1)>,
29				<NRF_PSEL(UART_RX, 1, 2)>;
30		};
31	};
32
33	uart1_sleep: uart1_sleep {
34		group1 {
35			psels = <NRF_PSEL(UART_TX, 1, 1)>,
36				<NRF_PSEL(UART_RX, 1, 2)>;
37			low-power-enable;
38		};
39	};
40
41	i2c1_default: i2c1_default {
42		group1 {
43			psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
44				<NRF_PSEL(TWIM_SCL, 0, 13)>;
45		};
46	};
47
48	i2c1_sleep: i2c1_sleep {
49		group1 {
50			psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
51				<NRF_PSEL(TWIM_SCL, 0, 13)>;
52			low-power-enable;
53		};
54	};
55
56	qspi_default: qspi_default {
57		group1 {
58			psels = <NRF_PSEL(QSPI_SCK, 1, 11)>,
59				<NRF_PSEL(QSPI_IO0, 1, 15)>,
60				<NRF_PSEL(QSPI_IO1, 1, 14)>,
61				<NRF_PSEL(QSPI_IO2, 1, 13)>,
62				<NRF_PSEL(QSPI_IO3, 1, 12)>,
63				<NRF_PSEL(QSPI_CSN, 1, 10)>;
64		};
65	};
66
67	qspi_sleep: qspi_sleep {
68		group1 {
69			psels = <NRF_PSEL(QSPI_SCK, 1, 11)>,
70				<NRF_PSEL(QSPI_IO0, 1, 15)>,
71				<NRF_PSEL(QSPI_IO1, 1, 14)>,
72				<NRF_PSEL(QSPI_IO2, 1, 13)>,
73				<NRF_PSEL(QSPI_IO3, 1, 12)>,
74				<NRF_PSEL(QSPI_CSN, 1, 10)>;
75			low-power-enable;
76		};
77	};
78
79};
80