1.. _mps2_an385_board:
2
3ARM V2M MPS2
4############
5
6Overview
7********
8
9The mps2_an385 board configuration is used by Zephyr applications that run on
10the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
11the following devices:
12
13- Nested Vectored Interrupt Controller (NVIC)
14- System Tick System Clock (SYSTICK)
15- Cortex-M System Design Kit UART
16
17.. image:: img/mps2_an385.jpg
18     :align: center
19     :alt: ARM V2M MPS2
20
21In addition to enabling actual hardware usage, this board configuration can
22also use QEMU to emulate the AN385 platform running on the MPS2+.
23
24More information about the board can be found at the `V2M MPS2 Website`_.
25
26The Application Note AN385 can be found at `Application Note AN385`_.
27
28.. note::
29   This board configuration makes no claims about its suitability for use
30   with actual MPS2 hardware systems using AN385, or any other hardware
31   system. It has been tested on actual hardware, but its primary purpose is
32   for use with QEMU and unit tests.
33
34Hardware
35********
36
37ARM V2M MPS2 provides the following hardware components:
38
39- ARM Cortex-M3 (AN385)
40- ARM IoT Subsystem for Cortex-M
41- Form factor: 140x120cm
42- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
43- Video: QSVGA touch screen panel, 4bit RGB VGA connector
44- Audio: Audio Codec
45- Debug:
46
47  - ARM JTAG20 connector
48  - ARM parallel trace connector (MICTOR38)
49  - 20 pin Cortex debug connector
50  - 10 pin Cortex debug connector
51  - ILA connector for FPGA debug
52
53- Expansion
54
55  - GPIO
56  - SPI
57
58.. note::
59   4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
60   (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
61
62Supported Features
63==================
64
65The mps2_an385 board configuration supports the following hardware features:
66
67+-----------+------------+-------------------------------------+
68| Interface | Controller | Driver/Component                    |
69+===========+============+=====================================+
70| NVIC      | on-chip    | nested vector interrupt controller  |
71+-----------+------------+-------------------------------------+
72| SYSTICK   | on-chip    | systick                             |
73+-----------+------------+-------------------------------------+
74| UART      | on-chip    | serial port-polling;                |
75|           |            | serial port-interrupt               |
76+-----------+------------+-------------------------------------+
77| GPIO      | on-chip    | gpio                                |
78+-----------+------------+-------------------------------------+
79| WATCHDOG  | on-chip    | watchdog                            |
80+-----------+------------+-------------------------------------+
81| TIMER     | on-chip    | counter                             |
82+-----------+------------+-------------------------------------+
83| DUALTIMER | on-chip    | counter                             |
84+-----------+------------+-------------------------------------+
85
86Other hardware features are not currently supported by the port.
87See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
88features.
89
90The default configuration can be found in the defconfig file:
91
92.. code-block:: console
93
94   boards/arm/mps2_an385/mps2_an385_defconfig
95
96Interrupt Controller
97====================
98
99MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs.
100
101A Cortex-M3/4-based board uses vectored exceptions. This means each exception
102calls a handler directly from the vector table.
103
104Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here
105identifies the handlers used for each exception.
106
107+------+------------+----------------+--------------------------+
108| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
109+======+============+================+==========================+
110| 1    | Reset      |                | system initialization    |
111+------+------------+----------------+--------------------------+
112| 2    | NMI        |                | system fatal error       |
113+------+------------+----------------+--------------------------+
114| 3    | Hard fault |                | system fatal error       |
115+------+------------+----------------+--------------------------+
116| 4    | MemManage  | MPU fault      | system fatal error       |
117+------+------------+----------------+--------------------------+
118| 5    | Bus        |                | system fatal error       |
119+------+------------+----------------+--------------------------+
120| 6    | Usage      | undefined      | system fatal error       |
121|      | fault      | instruction,   |                          |
122|      |            | or switch      |                          |
123|      |            | attempt to ARM |                          |
124|      |            | mode           |                          |
125+------+------------+----------------+--------------------------+
126| 11   | SVC        |                | system calls, kernel     |
127|      |            |                | run-time exceptions,     |
128|      |            |                | and IRQ offloading       |
129+------+------------+----------------+--------------------------+
130| 12   | Debug      |                | system fatal error       |
131|      | monitor    |                |                          |
132+------+------------+----------------+--------------------------+
133| 14   | PendSV     |                | context switch           |
134+------+------------+----------------+--------------------------+
135| 15   | SYSTICK    |                | system clock             |
136+------+------------+----------------+--------------------------+
137
138Pin Mapping
139===========
140
141The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
142for pin muxing, input/output, pull-up, etc.
143
144All GPIO controller pins are exposed via the following sequence of pin numbers:
145
146- Pins 0 - 15 are for GPIO 0
147- Pins 16 - 31 are for GPIO 1
148- Pins 32 -  47 are for GPIO 2
149- Pins 48 -  51 are for GPIO 3
150
151Mapping from the ARM MPS2 Board pins to GPIO controllers:
152
153.. rst-class:: rst-columns
154
155   - D0 : EXT_0
156   - D1 : EXT_4
157   - D2 : EXT_2
158   - D3 : EXT_3
159   - D4 : EXT_1
160   - D5 : EXT_6
161   - D6 : EXT_7
162   - D7 : EXT_8
163   - D8 : EXT_9
164   - D9 : EXT_10
165   - D10 : EXT_12
166   - D11 : EXT_13
167   - D12 : EXT_14
168   - D13 : EXT_11
169   - D14 : EXT_15
170   - D15 : EXT_5
171   - D16 : EXT_16
172   - D17 : EXT_17
173   - D18 : EXT_18
174   - D19 : EXT_19
175   - D20 : EXT_20
176   - D21 : EXT_21
177   - D22 : EXT_22
178   - D23 : EXT_23
179   - D24 : EXT_24
180   - D25 : EXT_25
181   - D26 : EXT_26
182   - D27 : EXT_30
183   - D28 : EXT_28
184   - D29 : EXT_29
185   - D30 : EXT_27
186   - D31 : EXT_32
187   - D32 : EXT_33
188   - D33 : EXT_34
189   - D34 : EXT_35
190   - D35 : EXT_36
191   - D36 : EXT_38
192   - D37 : EXT_39
193   - D38 : EXT_40
194   - D39 : EXT_44
195   - D40 : EXT_41
196   - D41 : EXT_31
197   - D42 : EXT_37
198   - D43 : EXT_42
199   - D44 : EXT_43
200   - D45 : EXT_45
201   - D46 : EXT_46
202   - D47 : EXT_47
203   - D48 : EXT_48
204   - D49 : EXT_49
205   - D50 : EXT_50
206   - D51 : EXT_51
207
208Peripheral Mapping:
209
210.. rst-class:: rst-columns
211
212   - UART_3_RX : D0
213   - UART_3_TX : D1
214   - SPI_3_CS : D10
215   - SPI_3_MOSI : D11
216   - SPI_3_MISO : D12
217   - SPI_3_SCLK : D13
218   - I2C_3_SDA : D14
219   - I2C_3_SCL : D15
220   - UART_4_RX : D26
221   - UART_4_TX : D30
222   - SPI_4_CS : D36
223   - SPI_4_MOSI : D37
224   - SPI_4_MISO : D38
225   - SPI_4_SCK : D39
226   - I2C_4_SDA : D40
227   - I2C_4_SCL : D41
228
229For mode details please refer to `MPS2 Technical Reference Manual (TRM)`_.
230
231System Clock
232============
233
234The V2M MPS2 main clock is 24 MHz.
235
236Serial Port
237===========
238
239The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
240RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
241default, is utilizing UART0.
242
243Programming and Debugging
244*************************
245
246Flashing
247========
248
249V2M MPS2 provides:
250
251- A USB connection to the host computer, which exposes a Mass Storage and an
252  USB Serial Port.
253- A Serial Flash device, which implements the USB flash disk file storage.
254- A physical UART connection which is relayed over interface USB Serial port.
255
256Flashing an application to V2M MPS2
257-----------------------------------
258
259Here is an example for the :ref:`hello_world` application.
260
261.. zephyr-app-commands::
262   :zephyr-app: samples/hello_world
263   :board: mps2_an385
264   :goals: build
265
266Connect the V2M MPS2 to your host computer using the USB port and you should
267see a USB connection which exposes a Mass Storage and a USB Serial Port.
268Copy the generated zephyr.bin in the exposed drive.
269Reset the board and you should be able to see on the corresponding Serial Port
270the following message:
271
272.. code-block:: console
273
274   Hello World! arm
275
276
277.. _V2M MPS2 Website:
278   https://developer.mbed.org/platforms/ARM-MPS2/
279
280.. _MPS2 Technical Reference Manual (TRM):
281   http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf
282
283.. _Application Note AN385:
284   http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf
285